Abstract Syntax Tree

Concept

An Abstract Syntax Tree (AST) is a tree-structured representation of the syntactic form of source code or formal artifacts. ASTs serve as an intermediate form between parsing and downstream analysis, transformation, and code generation; they are also a building block for syntactic filtering, machine-learning models on code, and declarative AST description tools.

First seen 6/9/2026

Last seen 8/4/2026

Evidence 5 chunks

Wiki v2

WIKI

Abstract Syntax Tree

An Abstract Syntax Tree (AST) is a hierarchical, tree-shaped data structure that represents the syntactic structure of a program, expression, or other formal artifact. Each node in the tree corresponds to a construct (e.g., an expression, statement, or instruction), and child nodes represent the operands or sub-constructs of their parent.

Role in Compilation and Code Generation

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NEIGHBORHOOD

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RELATIONSHIPS

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formal-iss code generation tool ← uses 100% 1e

The code generation tool generates a C/C++ AST as an intermediate representation

ChiGen ← uses 90% 1e

ChiGen uses an abstract syntax tree during constraint generation for type inference.

Hindley-Milner Type Inference ← uses 95% 1e

The Hindley-Milner type inference constraint generation follows a visitor-like traversal of the abstract syntax tree.

LINKED ENTITIES

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ChiGen USES Extracted graph relationship

Hindley-Milner Type Inference USES Extracted graph relationship

CITATIONS

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5 citations — click to expand

[1] ASTs are produced by front-end parsers and serve as the canonical intermediate representation that subsequent compiler phases (semantic analysis, optimization, code generation) operate on. Bottom-Up Generation of Verilog Designs for Testing EDA Tools

[2] In ChiGen, the Verible syntactic analyzer builds an abstract syntax tree for each candidate Verilog file; if it cannot, the file is discarded as syntactically invalid, and only survivors are sent to Jasper's more expensive semantic analyzer. Bottom-Up Generation of Verilog Designs for Testing EDA Tools

[3] ChiGen uses a Hindley-Milner-style type inference pipeline that creates type variables for each identifier, generates equality and conditional constraints (including Verilog bit-width extension rules), and solves them via unification; a unification failure (e.g., bitvector(8) vs bitvector(16)) causes the current Verilog skeleton to be discarded. Bottom-Up Generation of Verilog Designs for Testing EDA Tools

[4] Gom is a language for describing abstract syntax trees and generating a Java implementation for those trees, with the option to maintain the internal representation in canonical form with respect to a rewrite system so that client programs manipulate only normal forms. Canonical Abstract Syntax Trees

[5] BASTS (Block-wise Abstract Syntax Tree Splitting) splits code along dominator-tree blocks of its Control Flow Graph, produces a split AST per block, encodes each with a Tree-LSTM, and combines the resulting encodings with code encodings inside a Transformer to generate code summaries. Improving Code Summarization with Block-wise Abstract Syntax Tree Splitting