Page Table Randomization

Concept

Page table randomization is a verification feature in RISCV-DV, an open-source SystemVerilog/UVM instruction generator for RISC-V processor verification. Listed as "page table randomization and exception," it enables the generator to produce randomized page-table scenarios along with associated exception behavior for use in processor verification workloads.

First seen 5/25/2026

Last seen 8/4/2026

Evidence 3 chunks

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Page Table Randomization

Page table randomization is a verification feature of RISCV-DV, an open-source SystemVerilog/UVM-based instruction generator for RISC-V processor verification. In RISCV-DV, it is listed as "page table randomization and exception," meaning the generator can produce randomized page-table scenarios together with the corresponding exception behavior for inclusion in generated verification programs.^[1]^[2]^[3]

Context in RISCV-DV

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NEIGHBORHOOD

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RELATIONSHIPS

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riscv-dv ← implements 97% 2e

RISCV-DV supports page table randomization and exception

riscv-dv ← uses 1e

RISCV-DV uses page table randomization.

LINKED ENTITIES

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riscv-dv USES Extracted graph relationship

CITATIONS

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[1] Page table randomization is a feature of RISCV-DV, listed as 'page table randomization and exception' in the tool's feature list. chipsalliance/riscv-dv README

[2] RISCV-DV supports RV32IMAFDC and RV64IMAFDC instruction sets and machine, supervisor, and user privilege modes. chipsalliance/riscv-dv README

[3] RISCV-DV is implemented as a SystemVerilog/UVM 1.2-based instruction generator and is verified with Synopsys VCS, Cadence Incisive/Xcelium, Mentor Questa, and Aldec Riviera-PRO simulators. chipsalliance/riscv-dv README

[4] RISCV-DV source is obtained via 'git clone https://github.com/google/riscv-dv.git' and can be run through python3 run.py or installed as an editable Python package exposing 'run' and 'cov' commands. chipsalliance/riscv-dv README

[5] Page table randomization is grouped with other MMU/privileged features such as privileged CSR setup randomization, the privileged CSR test suite, trap/interrupt handling, and an MMU stress-test suite. chipsalliance/riscv-dv README

[6] RISCV-DV supports co-simulation with multiple instruction set simulators including Spike, riscv-ovpsim, Whisper, and sail-riscv. chipsalliance/riscv-dv README