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Page Table Randomization

Concept WIKI v2 · 8/4/2026

Page table randomization is a verification feature in RISCV-DV, an open-source SystemVerilog/UVM instruction generator for RISC-V processor verification. Listed as "page table randomization and exception," it enables the generator to produce randomized page-table scenarios along with associated exception behavior for use in processor verification workloads.

Page Table Randomization

Page table randomization is a verification feature of RISCV-DV, an open-source SystemVerilog/UVM-based instruction generator for RISC-V processor verification. In RISCV-DV, it is listed as "page table randomization and exception," meaning the generator can produce randomized page-table scenarios together with the corresponding exception behavior for inclusion in generated verification programs.[1][2][3]

Context in RISCV-DV

RISCV-DV targets both 32-bit and 64-bit RISC-V configurations, supporting the RV32IMAFDC and RV64IMAFDC instruction sets. It supports execution in machine mode, supervisor mode, and user mode, which is relevant because page-table behavior and memory-management-unit (MMU) behavior are exercised in privileged execution contexts.[1][2][3]

Page table randomization is grouped with other privileged-mode and MMU-oriented features within the tool:

  • Page table randomization and exception[1][2][3]
  • Privileged CSR setup randomization[1][2][3]
  • Privileged CSR test suite[1][2][3]
  • Trap and interrupt handling[1][2][3]
  • Test suite to stress test the MMU[1][2][3]
  • Sub-program generation and random program calls[1][2][3]
  • Illegal instruction and HINT instruction generation[1][2][3]
  • Random forward/backward branch instructions[1][2][3]
  • Mixing directed instructions with the random instruction stream[1][2][3]
  • Debug mode support with fully randomized debug ROM[1][2][3]
  • Instruction-generation coverage model[1][2][3]
  • Handshake / communication with the integrated SystemVerilog testbench[1][2][3]
  • Support for hand-coded assembly tests[1][2][3]
  • Co-simulation with multiple ISS: Spike, riscv-ovpsim, Whisper, sail-riscv[1][2]

Role in Verification

The page table randomization feature lets RISCV-DV users stress architectural and microarchitectural paths involved in virtual-to-physical address translation, including the page-walk logic, TLB behavior, and the exception paths triggered by page-table accesses. Combined with the MMU stress-test suite and trap/interrupt-handling generation, it forms part of a randomized stimulus flow that can exercise privileged-mode and translation-related corner cases in a RISC-V processor implementation.[1][2][3]

Implementation Environment

RISCV-DV is implemented in SystemVerilog with UVM 1.2. To run the instruction generator, an RTL simulator that supports SystemVerilog and UVM 1.2 is required. The project reports verification on Synopsys VCS, Cadence Incisive/Xcelium, Mentor Questa, and Aldec Riviera-PRO simulators.[1][3]

Obtaining and Running RISCV-DV

The source can be cloned from GitHub:

bash git clone https://github.com/google/riscv-dv.git

Two usage modes are documented: running the Python scripts directly:

bash pip3 install -r requirements.txt python3 run.py --help

or installing as an editable Python package:

bash export PATH=$HOME/.local/bin/:$PATH pip3 install --user -e .

After installation, RISCV-DV exposes run and cov commands.[1][3]

Related Entities

  • RISCV-DV — the open-source instruction generator that provides this feature and is its primary context.[1][2][3]

See Also

[1]: Evidence source ff810966-2ad0-414b-b040-4364dab496bc (chipsalliance/riscv-dv README): RISCV-DV project description and feature list. [2]: Evidence source 780b0092-53c5-473c-9a9c-8b1b539b0b42 (riscvschool.com article): RISCV-DV feature list, including "page table randomization and exception." [3]: Evidence source 3cf93dd9-a814-4325-a44a-decae348a236 (third_party/Surelog IbexGoogle README): RISCV-DV feature list and setup instructions, including "page table randomization and exception."

LINKED ENTITIES

1 links
riscv-dv USES

CITATIONS

6 sources
6 citations
[1] Page table randomization is a feature of RISCV-DV, listed as 'page table randomization and exception' in the tool's feature list. chipsalliance/riscv-dv README
[2] RISCV-DV supports RV32IMAFDC and RV64IMAFDC instruction sets and machine, supervisor, and user privilege modes. chipsalliance/riscv-dv README
[3] RISCV-DV is implemented as a SystemVerilog/UVM 1.2-based instruction generator and is verified with Synopsys VCS, Cadence Incisive/Xcelium, Mentor Questa, and Aldec Riviera-PRO simulators. chipsalliance/riscv-dv README
[4] RISCV-DV source is obtained via 'git clone https://github.com/google/riscv-dv.git' and can be run through python3 run.py or installed as an editable Python package exposing 'run' and 'cov' commands. chipsalliance/riscv-dv README
[5] Page table randomization is grouped with other MMU/privileged features such as privileged CSR setup randomization, the privileged CSR test suite, trap/interrupt handling, and an MMU stress-test suite. chipsalliance/riscv-dv README
[6] RISCV-DV supports co-simulation with multiple instruction set simulators including Spike, riscv-ovpsim, Whisper, and sail-riscv. chipsalliance/riscv-dv README

VERSION HISTORY

v2 · 8/4/2026 · minimax/minimax-m3 (current)
v1 · 5/25/2026 · gpt-5.5