Page Table Randomization

Page table randomization is a verification feature supported by RISCV-DV, an open-source SystemVerilog/UVM instruction generator for RISC-V processor verification. In RISCV-DV, it is listed as “page table randomization and exception,” indicating that the generator can create randomized page-table-related scenarios and associated exception behavior for processor verification workloads.^[1]

Context

RISCV-DV is designed to generate instruction streams for verifying RISC-V processors. It supports both RV32 and RV64 instruction-set configurations, specifically RV32IMAFDC and RV64IMAFDC, and it supports execution in machine mode, supervisor mode, and user mode.^[1] These privilege-mode capabilities are relevant because page-table behavior and memory-management-unit behavior are typically exercised in privileged execution contexts.

Role in Verification

Page table randomization is part of a broader set of RISCV-DV features intended to stress architectural and microarchitectural behavior. Related capabilities include:

Page table randomization and exception generation^[1]
Privileged CSR setup randomization^[1]
Trap and interrupt handling^[1]
A test suite to stress test the MMU^[1]
Random instruction generation, including branches, illegal instructions, and HINT instructions^[1]

Together, these features allow RISCV-DV users to generate randomized verification programs that can exercise translation, privilege, exception, and trap-handling paths in RISC-V processor implementations.

Implementation Environment

RISCV-DV is implemented as a SystemVerilog/UVM-based instruction generator.^[1] To run it, users need an RTL simulator with support for SystemVerilog and UVM 1.2. The project reports verification with several simulators, including Synopsys VCS, Cadence Incisive/Xcelium, Mentor Questa, and Aldec Riviera-PRO.^[1]

Usage in RISCV-DV

The RISCV-DV source can be obtained from GitHub:

git clone https://github.com/google/riscv-dv.git

The project can be used either by running Python scripts directly, such as:

pip3 install -r requirements.txt
python3 run.py --help

or by installing it as a Python package in editable mode:

export PATH=$HOME/.local/bin/:$PATH
pip3 install --user -e .

After installation, RISCV-DV can be invoked through its run and cov commands.^[1]

Related RISCV-DV Features

Page table randomization is one element of RISCV-DV’s broader verification feature set. Other supported features include sub-program generation, random program calls, directed-instruction mixing, debug-mode support with randomized debug ROM, instruction-generation coverage, testbench handshake communication, hand-coded assembly tests, and co-simulation with multiple instruction-set simulators, including Spike, riscv-ovpsim, Whisper, and Sail RISC-V.^[1]