Instruction Generation Coverage Model

Concept

The **Instruction Generation Coverage Model** is a functional coverage model that is part of **RISCV-DV**, an open-source UVM-based constrained-random instruction generator for RISC-V processor verification. The coverage model is tightly coupled to RISCV-DV's random generator engine and is used to measure functional coverage of the generated RISC-V instruction stream at the instruction, sequence, and program levels.[^adaf12ab][^a47aa5b1]

First seen 5/25/2026

Last seen 6/11/2026

Evidence 3 chunks

Wiki v2

WIKI

Instruction Generation Coverage Model

The Instruction Generation Coverage Model is a functional coverage model provided by RISCV-DV, an open-source instruction generator for RISC-V processor verification developed by Google.^[1] It is part of the UVM verification environment generated by RISCV-DV and is described as a "readily available functional coverage model for the ISA test suite."^[2]

Role in the RISCV-DV Verification Flow

READ FULL ARTICLE →

NEIGHBORHOOD

No graph connections found for this entity yet. It may appear in future ingestion runs.

explore full graph →

RELATIONSHIPS

1 connections

riscv-dv ← introduces 100% 1e

RISCV-DV provides an instruction generation coverage model for verification.

LINKED ENTITIES

1 links

riscv-dv INTRODUCES Extracted graph relationship

CITATIONS

9 sources

9 citations — click to expand

[1] RISCV-DV is an open-source instruction generator for RISC-V processor verification developed by Google, designed for UVM environments, supporting the base ISA and many extensions. Understanding UVM Coverage for RISC-V Processor Designs

[2] RISCV-DV provides instruction-level, sequence-level, and program-level randomization, helping obtain good stimulus coverage for the ISA test suite. Understanding UVM Coverage for RISC-V Processor Designs

[3] RISCV-DV generates a UVM testbench with a readily available functional coverage model for the ISA test suite, tightly coupled to the random generator engine that stress-tests the RISC-V core. Understanding UVM Coverage for RISC-V Processor Designs

[4] In the Bluespec MCU/MPU flow, functional coverage is enabled in the RISCV-DV testbench and code coverage is enabled in the MCU testbench; their databases are merged using Synopsys VCS URG or Verdi Coverage. Understanding UVM Coverage for RISC-V Processor Designs

[5] Defining 100% RISC-V ISA coverage is infeasible when crossing in source-register data values (2³² per operand); practical coverage models restrict the cross-product to modes, register addresses, register contents, and immediate values. Understanding UVM Coverage for RISC-V Processor Designs

[6] RISCV-DV supports mixed directed and random instruction streams, illegal/HINT instructions, random branches, sub-program and program-call generation, MMU/CSR/debug features, and co-simulation with Spike, riscv-ovpsim, Whisper, and Sail RISC-V. RISCV-DV README

[7] Running RISCV-DV requires an RTL simulator supporting SystemVerilog and UVM 1.2, verified with Synopsys VCS, Cadence Incisive/Xcelium, Mentor Questa, and Aldec Riviera-PRO. RISCV-DV README

[8] RISCV-DV can be cloned from https://github.com/google/riscv-dv and installed as an editable Python package via `pip3 install --user -e .`, exposing the `run` and `cov` commands. RISCV-DV README

[9] RISCV-DV has been contributed to CHIPS Alliance; it is not an officially supported Google product. RISCV-DV README