Instruction Generation Coverage Model

Concept

The **Instruction Generation Coverage Model** is a SystemVerilog functional coverage model shipped with RISCV-DV, Google's open-source SV/UVM-based instruction generator for RISC-V processor verification. The model is tightly coupled to RISCV-DV's random generator engine so that its covergroups track what the constrained-random stimulus actually produces, and it covers operands, hazards, corner cases, branches, hints/illegal opcodes, opcodes, privileged CSR accesses, and exceptions/interrupts.[^adaf12ab][^a47aa5b1][^3cf93dd9][^f1c1700d][^780b0092]

First seen 5/25/2026

Last seen 8/4/2026

Evidence 6 chunks

Wiki v3

WIKI

Instruction Generation Coverage Model

The Instruction Generation Coverage Model is a SystemVerilog functional coverage model provided by RISCV-DV, an open-source SV/UVM-based instruction generator for RISC-V processor verification.^[1]^[2] It is part of the UVM verification environment generated by RISCV-DV and is described in Synopsys documentation as a "readily available functional coverage model for the ISA test suite" that is "tightly coupled to the random generator engine that stress-tests the RISC-V core."^[3]

Relationship to RISCV-DV

READ FULL ARTICLE →

NEIGHBORHOOD

No graph connections found for this entity yet. It may appear in future ingestion runs.

explore full graph →

RELATIONSHIPS

3 connections

riscv-dv ← introduces 100% 1e

RISCV-DV provides an instruction generation coverage model for verification.

riscv-dv ← implements 97% 1e

RISCV-DV includes an instruction generation coverage model

riscv-dv ← uses 1e

RISCV-DV uses an instruction generation coverage model.

LINKED ENTITIES

1 links

riscv-dv USES Extracted graph relationship

CITATIONS

9 sources

9 citations — click to expand

[1] The Instruction Generation Coverage Model is part of the RISCV-DV feature set. RISCV-DV Processor Verification (riscvschool.com)

[2] The model is tightly coupled to the RISCV-DV random generator engine and is used as the functional coverage metric for the generated ISA test suite. Understanding UVM Coverage for RISC-V Processor Designs (Synopsys)

[3] Functional coverage is enabled in the RISCV-DV UVM testbench in the two-testbench MCU/MPU flow, with URG/Verdi used to merge functional and code coverage. Understanding UVM Coverage for RISC-V Processor Designs (Synopsys)

[4] RISCV-DV provides instruction-level, sequence-level, and program-level randomization. Understanding UVM Coverage for RISC-V Processor Designs (Synopsys)

[5] 100% RISC-V ISA coverage is mathematically not achievable when full data values are included; realistic coverage restricts the cross-product to a tractable set. Understanding UVM Coverage for RISC-V Processor Designs (Synopsys)

[6] The functional covergroup is defined in src/riscv_instr_cover_group.sv and includes coverpoints for operands, hazards, corner cases, aligned/unaligned accesses, immediates, branches, hints, illegal instructions, opcodes, privileged CSR access, and exceptions/interrupts. RISCV-DV IbexGoogle README (Surelog mirror)

[7] The covergroup is selectively instantiated based on riscv_core_setting.sv and is processed via cov.py against Spike simulation logs. RISCV-DV IbexGoogle README (Surelog mirror)

[8] RISCV-DV supports instruction sets RV32IMAFDC and RV64IMAFDC and co-simulates with Spike, riscv-ovpsim, Whisper, and Sail RISC-V. RISCV-DV Processor Verification (riscvschool.com)

[9] Running RISCV-DV requires a SystemVerilog/UVM 1.2 simulator; verified with Synopsys VCS, Cadence Incisive/Xcelium, and Mentor Questa. RISCV-DV README (Surelog mirror)