Skip to content
STIMSMITH

Instruction Generation Coverage Model

Concept WIKI v2 · 6/11/2026

The **Instruction Generation Coverage Model** is a functional coverage model that is part of **RISCV-DV**, an open-source UVM-based constrained-random instruction generator for RISC-V processor verification. The coverage model is tightly coupled to RISCV-DV's random generator engine and is used to measure functional coverage of the generated RISC-V instruction stream at the instruction, sequence, and program levels.[^adaf12ab][^a47aa5b1]

Instruction Generation Coverage Model

The Instruction Generation Coverage Model is a functional coverage model provided by RISCV-DV, an open-source instruction generator for RISC-V processor verification developed by Google.[1] It is part of the UVM verification environment generated by RISCV-DV and is described as a "readily available functional coverage model for the ISA test suite."[2]

Role in the RISCV-DV Verification Flow

RISCV-DV consists of two cooperating generators:[1]

  • A UVM testbench generator that produces constrained-random, ISA-based stimulus.
  • An assembly language generator that emits assembly files corresponding to that stimulus, which are converted into binary executables of random valid RISC-V instructions.[1]

The Instruction Generation Coverage Model is tightly coupled to the random generator engine that stress-tests the RISC-V core, so that the functional coverage points track the stimulus that the generator actually produces.[2] The RISCV-DV environment provides randomization at three levels, all of which are reflected in the coverage model:[1]

  • Instruction level randomization
  • Sequence level randomization
  • Program level randomization

Because of this coupling, the same coverage model can be reused as the functional coverage metric for downstream RISC-V implementations that are driven by RISCV-DV.[2]

Coverage Flow in a Typical Deployment

In a typical deployment (illustrated by the Bluespec MCU reference flow in the Synopsys white paper), the MCU/MPU simulation environment is split across two testbenches:[2]

  • MCU testbench — the top-level testbench in which the device-under-test RTL is simulated with Synopsys VCS. Code coverage is enabled here, and stimulus can come either from hand-written bring-up tests or from the constrained-random stream produced by RISCV-DV.
  • RISCV-DV testbench — a UVM testbench that generates constrained-random RISC-V instructions. Functional coverage is enabled in this testbench, using the Instruction Generation Coverage Model. The stimulus generated here is forwarded to the MCU testbench, and a Spike ISS run in the same environment produces the golden reference for result comparison.[2]

Synopsys VCS is used for simulation and Synopsys Verdi is used to view waveforms and coverage. The functional coverage database produced by the RISCV-DV testbench is merged with the code coverage database produced by the MCU testbench using the Synopsys VCS Unified Report Generator (URG) or Synopsys Verdi Coverage, and the merged database is then viewed in Verdi.[2]

Defining "100% RISC-V ISA Coverage"

Functional coverage definitions for RISC-V implementations aim to cover compliance to the ISA specification, ideally spanning all possible instruction combinations. Because the full mathematical space is not practically closable (for example, each 32-bit source register has 2³² possible data values), realistic coverage models — including the RISCV-DV model — restrict the cross-product to a tractable set of values.[2]

For an RV32I instruction, coverage points can be enumerated over modes, register addresses, register contents, and immediate values. With 32 architectural registers, register-address combinations are small (for an instruction with two source registers and one destination register, the register cross-product is 32×32×32 = 2¹⁵ combinations, which is within practical simulation reach). Crossing in the data values carried by those registers, however, multiplies the space by 2³² per source operand, which "explodes" the number of coverage points beyond practical limits.[2]

The Synopsys white paper illustrates, for addition and load instructions, columns for Possible Register Values, Possible Data Values, Possible Immediate Values, Mathematically Possible Coverage, a Practical Coverage target, RISCV-DV Coverage (what the shipped model achieves), and an Improved Coverage achieved by augmenting or refining the model.[2]

Background: RISCV-DV

RISCV-DV is described in the Synopsys white paper as "an instruction generator for RISC-V processor verification developed by Google and available as open-source." It is designed for use in UVM verification environments, generating handshakes between the generated code and the testbench, as well as the instruction generation coverage model. It supports the RISC-V base ISA and many of the standard extensions.[1]

Related RISCV-DV Capabilities

The Instruction Generation Coverage Model is one feature among RISCV-DV's broader verification capabilities, which also include:[3]

  • Mixed directed and random instruction streams, illegal and HINT instruction generation, random forward/backward branches, sub-program generation, and random program calls
  • Page-table randomization and exception generation
  • Privileged CSR setup randomization and privileged CSR test suites
  • Trap and interrupt handling
  • MMU stress-test suites
  • Debug-mode support with randomized debug ROM
  • Handshake communication with a testbench
  • Support for hand-coded assembly tests
  • Co-simulation with multiple instruction-set simulators, including Spike, riscv-ovpsim, Whisper, and Sail RISC-V

Tool and Environment Requirements

Running RISCV-DV requires an RTL simulator that supports SystemVerilog and UVM 1.2.[3] The generator has been verified with Synopsys VCS, Cadence Incisive/Xcelium, Mentor Questa, and Aldec Riviera-PRO simulators.[3]

Obtaining and Running RISCV-DV

The RISCV-DV source can be cloned from GitHub:[3]

git clone https://github.com/google/riscv-dv.git

For developer workflows:[3]

pip3 install -r requirements.txt
python3 run.py --help

For normal users, RISCV-DV can be installed as an editable Python package:[3]

export PATH=$HOME/.local/bin/:$PATH
pip3 install --user -e .

This makes repository changes immediately available through the run and cov commands without reinstalling the package after each change.[3]

Documentation and Project Status

RISCV-DV includes additional documentation under its docs directory, and a prebuilt HTML version is available at docs/build/singlehtml/index.html in the repository.[3] The project has been contributed to CHIPS Alliance, and the project documentation states that RISCV-DV is not an officially supported Google product.[3]

References

[1]: Synopsys white paper, "Understanding UVM Coverage for RISC-V Processor Designs." Evidence IDs adaf12ab-248f-41d3-a1ef-32bc406b7983 (background, RISCV-DV overview, randomization levels, golden reference, deployment context). [2]: Synopsys white paper, "Understanding UVM Coverage for RISC-V Processor Designs." Evidence IDs a47aa5b1-e129-40a8-8e43-8e466be8a8dd (coupling of the coverage model to the random generator, two-testbench MCU/MPU flow, merge with code coverage via URG/Verdi, 100% RISC-V ISA coverage discussion). [3]: Evidence ID ff810966-2ad0-414b-b040-4364dab496bc (RISCV-DV README: features, simulator requirements, install/run commands, CHIPS Alliance status).

LINKED ENTITIES

1 links
riscv-dv INTRODUCES

CITATIONS

9 sources
9 citations
[1] RISCV-DV is an open-source instruction generator for RISC-V processor verification developed by Google, designed for UVM environments, supporting the base ISA and many extensions. Understanding UVM Coverage for RISC-V Processor Designs
[2] RISCV-DV provides instruction-level, sequence-level, and program-level randomization, helping obtain good stimulus coverage for the ISA test suite. Understanding UVM Coverage for RISC-V Processor Designs
[3] RISCV-DV generates a UVM testbench with a readily available functional coverage model for the ISA test suite, tightly coupled to the random generator engine that stress-tests the RISC-V core. Understanding UVM Coverage for RISC-V Processor Designs
[4] In the Bluespec MCU/MPU flow, functional coverage is enabled in the RISCV-DV testbench and code coverage is enabled in the MCU testbench; their databases are merged using Synopsys VCS URG or Verdi Coverage. Understanding UVM Coverage for RISC-V Processor Designs
[5] Defining 100% RISC-V ISA coverage is infeasible when crossing in source-register data values (2³² per operand); practical coverage models restrict the cross-product to modes, register addresses, register contents, and immediate values. Understanding UVM Coverage for RISC-V Processor Designs
[6] RISCV-DV supports mixed directed and random instruction streams, illegal/HINT instructions, random branches, sub-program and program-call generation, MMU/CSR/debug features, and co-simulation with Spike, riscv-ovpsim, Whisper, and Sail RISC-V. RISCV-DV README
[7] Running RISCV-DV requires an RTL simulator supporting SystemVerilog and UVM 1.2, verified with Synopsys VCS, Cadence Incisive/Xcelium, Mentor Questa, and Aldec Riviera-PRO. RISCV-DV README
[8] RISCV-DV can be cloned from https://github.com/google/riscv-dv and installed as an editable Python package via `pip3 install --user -e .`, exposing the `run` and `cov` commands. RISCV-DV README
[9] RISCV-DV has been contributed to CHIPS Alliance; it is not an officially supported Google product. RISCV-DV README

VERSION HISTORY

v2 · 6/11/2026 · minimax/minimax-m3 (current)
v1 · 5/25/2026 · gpt-5.5