Instruction Generation Coverage Model

The Instruction Generation Coverage Model is a SystemVerilog functional coverage model provided by RISCV-DV, an open-source SV/UVM-based instruction generator for RISC-V processor verification.^[1]^[2] It is part of the UVM verification environment generated by RISCV-DV and is described in Synopsys documentation as a "readily available functional coverage model for the ISA test suite" that is "tightly coupled to the random generator engine that stress-tests the RISC-V core."^[3]

Relationship to RISCV-DV

The Instruction Generation Coverage Model is one of RISCV-DV's documented features. The RISCV-DV feature list explicitly enumerates "Instruction generation coverage model" alongside:

Supported instruction sets: RV32IMAFDC and RV64IMAFDC^[1]^[2]
Supported privileged modes: machine, supervisor, and user mode^[1]^[2]
Page-table randomization and exception generation^[1]^[2]
Privileged CSR setup randomization and a privileged CSR test suite^[1]^[2]
Trap/interrupt handling and an MMU stress-test suite^[1]^[2]
Sub-program generation and random program calls^[1]^[2]
Illegal-instruction and HINT-instruction generation^[1]^[2]
Random forward/backward branch instructions and mixing of directed instructions with a random instruction stream^[1]^[2]
Debug-mode support with a fully randomized debug ROM^[1]^[2]
Communication of information to any integrated SV testbench (handshake mechanism)^[2]
Co-simulation with multiple ISSs: Spike, riscv-ovpsim, Whisper, and Sail RISC-V^[1]^[2]
Support for hand-coded assembly tests^[1]

Because the model is generated as part of the same UVM testbench that produces the constrained-random instruction stream, its coverage points track the stimulus the generator actually emits.^[3]

Coverage Groups and Categories

The functional covergroup is defined in src/riscv_instr_cover_group.sv in the RISCV-DV repository.^[4] It includes the following major coverpoint categories:^[4]

All operands for each instruction
Hazard conditions
Corner cases such as overflow, underflow, and divide by zero
Aligned/unaligned load/store
Positive/negative immediate values
Forward/backward branches and branch-hit history
Hint instructions
Illegal instructions
All compressed and non-compressed opcodes
Access to all implemented privileged CSRs
Exceptions and interrupts

The covergroup is selectively instantiated based on setting/riscv_core_setting.sv, which describes the processor's capabilities, so that only relevant coverpoints need to be considered.^[4] The covergroup is described as "still under active development" in the documentation, with users invited to extend it or file bug requests.^[4]

Role in the RISCV-DV Verification Flow

The Instruction Generation Coverage Model is integrated into the standard RISCV-DV flow:^[5]^[3]

The RISCV-DV environment provides instruction-level, sequence-level, and program-level randomization, and produces assembly files that are converted into binary executables of random valid RISC-V instructions.^[5]^[3]
Functional coverage is enabled in the RISCV-DV UVM testbench, so that the same model that drives stimulus generation also measures how much of the ISA stimulus space has been exercised.^[3]
A Spike (or other ISS) run in the same environment produces the golden reference for result comparison against the RTL design.^[5]

Because the model is tightly coupled to the generator, the same coverage model can be reused as the functional coverage metric for downstream RISC-V implementations driven by RISCV-DV.^[3]

Coverage Flow in a Typical Deployment

In the Bluespec MCU/MPU verification environment described in the Synopsys white paper, the simulation environment is split across two testbenches:^[3]

MCU testbench — the top-level testbench in which the device-under-test RTL is simulated with Synopsys VCS. Code coverage is enabled here, and stimulus can come either from hand-written bring-up tests or from the constrained-random stream produced by RISCV-DV.^[3]
RISCV-DV testbench — a UVM testbench that generates constrained-random RISC-V instructions. Functional coverage is enabled in this testbench using the Instruction Generation Coverage Model. The stimulus generated here is forwarded to the MCU testbench, and a Spike ISS run in the same environment produces the golden reference for result comparison.^[3]

Synopsys VCS is used for simulation and Synopsys Verdi is used to view waveforms and coverage.^[5] The functional-coverage database produced by the RISCV-DV testbench is merged with the code-coverage database produced by the MCU testbench using the Synopsys VCS Unified Report Generator (URG) or Synopsys Verdi Coverage, and the merged database is then viewed in Verdi.^[3]

Defining "100% RISC-V ISA Coverage"

Functional-coverage definitions for RISC-V implementations aim to cover compliance with the ISA specification, ideally spanning all possible instruction combinations. Because the full mathematical space is not practically closable (for example, each 32-bit source register has 2^32 possible data values), realistic coverage models — including the RISCV-DV model — restrict the cross-product to a tractable set of values.^[3]

For an RV32I instruction, coverage points can be enumerated over modes, register addresses, register contents, and immediate values. With 32 architectural registers, register-address combinations are small (for an instruction with two source registers and one destination register, the register cross-product is 32×32×32 = 2^15 combinations, which is within practical simulation reach). Crossing in the data values carried by those registers, however, multiplies the space by 2^32 per source operand, which "explodes" the number of coverage points beyond practical limits.^[3]

The Synopsys white paper illustrates, for addition and load instructions, columns for Possible Register Values, Possible Data Values, Possible Immediate Values, Mathematically Possible Coverage, a Practical Coverage target, RISCV-DV Coverage (what the shipped model achieves), and an Improved Coverage achieved by augmenting or refining the model.^[3]

Running the Coverage Flow

The coverage flow uses Spike's commit log as the source of functional-coverage events:^[4]

Build Spike with --enable-commitlog and set SPIKE_PATH.^[4]
Run the instruction generator to produce a Spike simulation log.^[4]
Process the Spike log and sample functional coverage:^[4]

bash

Process spike simulation log and collect functional coverage

python3 cov.py --dir out/spike_sim

Run the coverage flow with predefined targets

python3 cov.py --dir out/spike_sim --target rv32imc

The documentation notes that sampling from CSV can be time-consuming for large logs and recommends splitting them into small batches run in parallel via LSF.^[4]

Tool and Environment Requirements

Running RISCV-DV (and therefore the Instruction Generation Coverage Model) requires an RTL simulator that supports SystemVerilog and UVM 1.2.^[2] The generator has been verified with Synopsys VCS, Cadence Incisive/Xcelium, and Mentor Questa simulators.^[2]

Related RISCV-DV Capabilities

In addition to the Instruction Generation Coverage Model, RISCV-DV provides:^[1]^[2]^[4]

A handshake mechanism that allows the generator to write critical information to a specified memory address, which the testbench monitors for write accesses, enabling more in-depth verification of external-stimulus scenarios such as interrupts and debug requests.^[4]
An end-to-end RTL/ISS co-simulation flow developed in collaboration with LowRISC for the IBEX RISC-V core, demonstrating how to extend RISCV-DV (e.g., via user_extension/ and +uvm_set_type_override) without modifying upstream classes.^[4]
A Python-based CSR test-generation script that produces a directed test suite stressing all CSR instructions on every implemented CSR.^[2]

References

^[5]: Synopsys white paper, "Understanding UVM Coverage for RISC-V Processor Designs." Evidence IDs adaf12ab-248f-41d3-a1ef-32bc406b7983 (RISCV-DV background, randomization levels, golden reference, two-testbench deployment context). ^[3]: Synopsys white paper, "Understanding UVM Coverage for RISC-V Processor Designs." Evidence ID a47aa5b1-e129-40a8-8e43-8e466be8a8dd (coupling of the coverage model to the random generator, two-testbench MCU/MPU flow, merge with code coverage via URG/Verdi, 100% RISC-V ISA coverage discussion). ^[2]: RISCV-DV README excerpt. Evidence ID 3cf93dd9-a814-4325-a44a-decae348a236 (feature list including instruction generation coverage model, simulator/prerequisites, running the generator). ^[4]: RISCV-DV IbexGoogle README excerpt. Evidence ID f1c1700d-e9bb-4b4a-8189-7f75aaa99ce1 (functional-covergroup categories defined in riscv_instr_cover_group.sv, riscv_core_setting.sv-based instantiation, handshake mechanism, end-to-end IBEX co-simulation flow, cov.py usage). ^[1]: RISC-V School blog post, "RISCV-DV Processor Verification." Evidence ID 780b0092-53c5-473c-9a9c-8b1b539b0b42 (feature list enumerating instruction generation coverage model and supporting ISS list).