2026-08-03
6 items 187 entities 209 connections
Processed 20 entities and 22 relations.
RISC-V CPU Core (ultraembedded/riscv) biRISC-V RV32IM RISC-V ISA RISCV-DV exactstep co-simulation random instruction sequence generation Verilator System-C testbench instruction set simulator pipelined CPU MMU AXI bus interface tightly coupled memory set associative cache Google FPGA riscv_tcm_top.v riscv_top.v
Processed 35 entities and 38 relations.
RISC-V Opcodes Repository RISC-V instruction opcodes RISC-V control and status registers instruction encoding regular instruction pseudo-op instruction imported instruction opcode bit encoding mask match variable fields unratified extension canonical ordering encoding.h parse.py instr_dict.json instr-table.tex priv-instr-table.tex inst.chisel inst.sverilog inst.rs inst.spinalhdl inst.go Spike PK uv RISC-V Manual RISC-V rv32 rv64 RISC-V I extension RISC-V M extension artifact generation instr_dict
Processed 17 entities and 19 relations.
GenHuzz hardware fuzz testing whitebox fuzzing Hardware-Guided Reinforcement Learning language model-based fuzzer RISC-V assembly instruction generation fuzzing policy optimization hardware coverage RISC-V hardware vulnerability detection Lichao Wu Mohamadreza Rostami Huimin Li Jeyavijayan Rajendran Ahmad-Reza Sadeghi GenHuzz paper USENIX
Processed 21 entities and 20 relations.
Processed 33 entities and 35 relations.
RISC-V Verification Interface (RVVI) RVVI-TRACE RVVI-TEXT RVVI-API RVVI-VVP RISC-V Formal Interface (RVFI) Hardware Design Verification (HW DV) RTL test bench reference model functional coverage stimulus generation virtual verification peripherals asynchronous interrupts Out-of-Order execution multi-hart SystemVerilog DPI instruction set simulator (ISS) ImperasDV Verilator Xcelium VCS Questa Imperas EMMicro SiLabs OpenHW Group SymbioticEDA Synopsys Cadence Siemens EDA CV32E40X core-v-verif
Processed 61 entities and 75 relations.
CASCADE Side Channel Analysis Simple Power Analysis Differential Power Analysis Correlation Power Analysis Mutual Information Analysis Test Vector Leakage Assessment Exhaustive Dynamic Power Capturing Marching-Sticks Model Hamming Distance Model Instantaneous Power Consumption Simulation Composite Current Source Models Delta-Delay Model Zero-Delay Model SPICE Simulation Standard-Cell Design Flow Threshold Implementation Wave Dynamic Differential Logic Domain-Oriented Masking Masking Logic Simulation Physical Simulation Test Bench Generation Pseudo-Random Input Sequence Generation Fixed vs. Random TVLA Welch's T-Test Higher-Order Statistical Moment Analysis Measurement to Disclosure Instantaneous Power Consumption Power Frame File Analyzed Frame Data Standard Delay Format Open Liberty Format Pre-Silicon Evaluation Simulation Frame Synopsys Design Compiler Cadence Innovus MentorGraphics QuestaSim Synopsys PrimeTime PX Synopsys HSPICE Test Bench Generator Delay Generator SPICE Generator Logic Parser Power Parser SPICE Parser Session Manager Library Manager TVLA Analyzer AES-128 Unrolled Implementation TI PRESENT S-Box WDDL PRESENT S-Layer Danilo Sijacic Josep Balasch Bohan Yang Santosh Ghosh Ingrid Verbauwhede imec-COSIC KU Leuven Intel Labs Towards Efficient and Automated Side Channel Evaluations at Design Time Synopsys PrimeTime PX