AES-128 Unrolled Implementation

Concept

The AES-128 unrolled implementation (AES-U) is a fully unrolled AES-128 hardware design used as a scalability benchmark for the CASCADE side-channel evaluation framework. With a placed and routed area of 127.18 kGE, it exceeds typical security-dedicated area budgets for embedded devices, and is used to demonstrate that one million traces can be simulated and analyzed within practical runtimes on a standard workstation.

First seen 8/3/2026

Last seen 8/3/2026

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AES-128 Unrolled Implementation

The AES-128 Unrolled Implementation (abbreviated AES-U in the CASCADE benchmark suite) is a fully unrolled hardware realization of the AES-128 block cipher. It was designed specifically as a stress-test / scalability case study for evaluating side-channel leakage assessment at the design stage, rather than as a compact implementation suited to embedded deployment.

Design characteristics

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Cascade ← evaluates 100% 1e

CASCADE is applied to a fully unrolled AES-128 implementation for scalability testing.

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CITATIONS

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[1] AES-U is a fully unrolled AES-128 hardware implementation with a placed and routed area of 127.18 kGE. Towards Efficient and Automated Side Channel Evaluations at Design Time

[2] AES-U simulations are performed at the post-layout stage with extracted layout parasitics, using CCS models with a precision of 1 ps and a frame size of 30,000 ps. Towards Efficient and Automated Side Channel Evaluations at Design Time

[3] The 127.18 kGE area of AES-U exceeds security-dedicated area budgets of many embedded devices. Towards Efficient and Automated Side Channel Evaluations at Design Time

[4] For 1 million PAR traces of AES-U on a single thread of an i7-7700, reported runtimes are LSIM 25.81 h, LP 5.75 h, TVLA1 0.16 h, and TVLA2 0.26 h. Towards Efficient and Automated Side Channel Evaluations at Design Time

[5] On a single thread of the i7-7700, one million AES-U traces can be simulated and processed in less than 32 hours; on 8 threads of the same workstation, the workload completes in less than 4 hours. Towards Efficient and Automated Side Channel Evaluations at Design Time

[6] AES-U simulations can be parallelized in batches of 10,000 to 100,000 frames without significant performance difference, and CASCADE performs all leakage analysis on the fly so that LSIM trace dumps are not stored. Towards Efficient and Automated Side Channel Evaluations at Design Time

[7] CASCADE is a comprehensive framework for SCA evaluation at design time that uses TVLA on the fly, following the approach of Schneider and Moradi. Towards Efficient and Automated Side Channel Evaluations at Design Time