AXI Bus Interface
ConceptAXI is one of several configurable on-chip bus interface options commonly exposed as a microarchitectural parameter in highly parameterizable RISC-V RTL cores, alongside AHB and TL-UL.
First seen 6/21/2026
Last seen 6/21/2026
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AXI Bus Interface
Definition
In the context of parameterizable RISC-V processor RTL, AXI refers to the Advanced eXtensible Interface bus protocol used as an on-chip interconnect between the core and external memory or peripherals. It is exposed as a selectable bus interface option at the microarchitectural level.
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1 connectionsAXI bus interface is one of the selectable bus interface options in the parameterization scheme.
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[1] AXI is listed as one of the configurable bus interface options (alongside AHB and TL-UL) in a parameterizable RISC-V RTL core's microarchitectural knobs. Inside RISC-V: Navigating the RTL Design & Verification Landscape