AXI Bus Interface

Concept

The AXI bus interface is an on-chip interconnect option exposed by the ultraembedded/riscv 32-bit RISC-V core (RV32IMZicsr) and its example wrapper modules. The core supports selectable integration via AXI (including AXI4 master ports for instruction/data caches and AXI4/AXI4-Lite ports in the TCM example), with AXI, AHB, and TL-UL commonly cited as configurable bus interface microarchitectural options in parameterizable RISC-V RTL design.

First seen 6/21/2026

Last seen 8/3/2026

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AXI Bus Interface

Definition

AXI (Advanced eXtensible Interface) is an AMBA on-chip bus protocol used to connect a processor core to external memory and peripherals. In the context of the ultraembedded/riscv core, AXI is exposed as one of the selectable bus interface options for integrating the 32-bit RV32IMZicsr CPU into a System-on-Chip.

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RELATIONSHIPS

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RISC-V CPU Core (ultraembedded/riscv) ← implements 97% 2e

The core supports AXI bus interfaces for memory access.

riscv_tcm_top.v ← implements 96% 2e

riscv_tcm_top.v adds AXI bus interfaces to the core instance.

Parameterization part of → 88% 1e

AXI bus interface is one of the selectable bus interface options in the parameterization scheme.

riscv_top.v ← implements 96% 1e

riscv_top.v exposes AXI4 master interfaces for CPU memory access.

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RISC-V CPU Core (ultraembedded/riscv) IMPLEMENTS Extracted graph relationship

riscv_tcm_top.v IMPLEMENTS Extracted graph relationship

riscv_top.v IMPLEMENTS Extracted graph relationship

CITATIONS

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[1] AXI is listed as one of the supported integration options (alongside caches and tightly coupled memories) of the ultraembedded/riscv 32-bit RV32IMZicsr core. ultraembedded/riscv

[2] The riscv_tcm_top.v wrapper exposes an AXI4 slave interface (axi_t_*) for the 64KB TCM and an AXI4-Lite master interface (axi_i_*) for peripherals, with independent reset of memory/AXI vs. CPU core. ultraembedded/riscv

[3] The riscv_top.v (cache-based) wrapper exposes two AXI4 master ports (axi_i_* for instruction memory, axi_d_* for data/peripheral memory) around 16KB 2-way set-associative I-cache and D-cache (write-back, allocate-on-write). ultraembedded/riscv

[4] In parameterizable RISC-V RTL design, AXI, AHB, and TL-UL are listed as selectable bus interface microarchitectural options alongside other knobs like XLEN, ISA extensions, pipeline depth, branch predictor structure, and cache associativity. Inside RISC-V: Navigating the RTL Design & Verification Landscape