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AXI Bus Interface

Concept WIKI v1 · 6/21/2026

AXI is one of several configurable on-chip bus interface options commonly exposed as a microarchitectural parameter in highly parameterizable RISC-V RTL cores, alongside AHB and TL-UL.

AXI Bus Interface

Definition

In the context of parameterizable RISC-V processor RTL, AXI refers to the Advanced eXtensible Interface bus protocol used as an on-chip interconnect between the core and external memory or peripherals. It is exposed as a selectable bus interface option at the microarchitectural level.

Role in Parameterizable RTL Design

AXI is typically one of several bus interface choices that a RISC-V core's RTL can be configured to expose. The RISC-V RTL design methodology treats the bus interface as a microarchitectural knob, alongside other configurable parameters such as:

  • XLEN (32, 64, or 128)
  • Selectable ISA extensions (M, C, F/D, custom X)
  • Pipeline depth
  • Branch predictor structure (BHT vs. BTB sizes)
  • Cache associativity

Commonly co-listed bus interface options alongside AXI include AHB and TL-UL, allowing designers to select the protocol that best matches their SoC integration requirements.

Parameterization Context

Bus interface selection (AXI, AHB, or TL-UL) falls under the broader concept of parameterization in RTL design, where architectural features are made configurable rather than fixed at synthesis time. This enables a single RTL codebase to target multiple SoC platforms and integration scenarios.

Related Concepts

  • Parameterization: The design methodology that enables AXI to be selected as one of multiple bus interface options.

LINKED ENTITIES

1 links
Parameterization PART_OF

CITATIONS

1 sources
1 citations
[1] AXI is listed as one of the configurable bus interface options (alongside AHB and TL-UL) in a parameterizable RISC-V RTL core's microarchitectural knobs. Inside RISC-V: Navigating the RTL Design & Verification Landscape