AXI Bus Interface
Definition
AXI (Advanced eXtensible Interface) is an AMBA on-chip bus protocol used to connect a processor core to external memory and peripherals. In the context of the ultraembedded/riscv core, AXI is exposed as one of the selectable bus interface options for integrating the 32-bit RV32IMZicsr CPU into a System-on-Chip.
Usage in the ultraembedded/riscv Core
The ultraembedded/riscv project explicitly lists AXI among its supported integration options. Per the project's feature list, the core offers:
- Configurable integration via instruction / data cache, AXI bus interfaces, or tightly coupled memories (TCM).
This selection affects how the core's memory subsystem is wired to the rest of the SoC.
Example Wrappers Exposing AXI
Two reference top-level wrappers in the repository demonstrate how AXI is instantiated around the core:
1. TCM + AXI Wrapper — riscv_tcm_top.v
This wrapper (top_tcm_axi/src_v) instantiates the core with 64KB of dual-ported RAM and standard bus interfaces. Its AXI port set is:
axi_t_*— AXI4 slave interface for external access to the 64KB TCM memory (including DMA-style loading and burst access support).axi_i_*— AXI4-Lite master interface for CPU access to peripherals.
The address map exposed through these interfaces is:
| Range | Description |
|---|---|
0x0000_0000 – 0x0000_ffff |
64KB TCM Memory |
0x0000_2000 |
Boot address (configurable via RISCV_BOOT_ADDRESS) |
0x8000_0000 – 0xffff_ffff |
Peripheral address space (served over the AXI4-Lite master port) |
The reset structure is split so that memory/AXI logic and the CPU core can be brought out of reset independently — program code can be loaded over the AXI4 slave port before the CPU reset is de-asserted:
| Signal | Description |
|---|---|
clk_i |
Clock input |
rst_i |
Async reset, active-high. Resets memory / AXI interface. |
rst_cpu_i |
Async reset, active-high. Resets the CPU core (excluding AXI / memory). |
intr_i |
Active-high interrupt input. |
2. Cache + AXI Wrapper — riscv_top.v
This wrapper (top_cache_axi/src_v) instantiates the core with 16KB 2-way set-associative instruction and data caches (data cache is write-back, allocate-on-write) and exposes two AXI4 master ports:
axi_i_*— AXI4 master for CPU instruction fetch from memory.axi_d_*— AXI4 master for CPU data accesses and peripheral accesses.
AXI as a Microarchitectural Knob in Parameterizable RISC-V RTL
In broader parameterizable RISC-V RTL design, the bus interface is treated as a configurable microarchitectural parameter alongside other knobs such as XLEN, selectable ISA extensions (M, C, F/D, custom X), pipeline depth, branch predictor structure (BHT vs. BTB sizes), and cache associativity. The protocols commonly co-listed as selectable bus options are AXI, AHB, and TL-UL, allowing designers to pick the protocol best matching their SoC integration requirements.
Related Concepts
- Parameterization — The RTL design methodology that allows AXI (vs. AHB or TL-UL) to be selected at synthesis/configuration time.
- Tightly Coupled Memory (TCM) — An alternative to cache+AXI integration in ultraembedded/riscv, often combined with an AXI4 slave port for code loading.