riscv_top.v

CodeArtifact

First seen 8/3/2026

Last seen 8/3/2026

Evidence 1 chunks

NEIGHBORHOOD

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3 connections

set associative cache implements → 97% 1e

riscv_top.v instantiates the core with 2-way set associative instruction and data caches.

AXI Bus Interface implements → 96% 1e

riscv_top.v exposes AXI4 master interfaces for CPU memory access.

riscv_top.v is the top-level file in the riscv repository for the cache-based core instance.