RISC-V CPU Core (ultraembedded/riscv)

Tool

First seen 8/3/2026

Last seen 8/3/2026

Evidence 2 chunks

NEIGHBORHOOD

No graph connections found for this entity yet. It may appear in future ingestion runs.

14 connections

System-C testbench ← evaluates 96% 2e

The System-C testbench is used to test the RISC-V CPU core.

AXI Bus Interface implements → 97% 2e

The core supports AXI bus interfaces for memory access.

Pipelined CPU implements → 97% 1e

The core is a pipelined RISC-V CPU with configurable pipeline stages.

MMU implements → 97% 1e

The core includes basic MMU support capable of booting Linux.

tightly coupled memory implements → 97% 1e

The core supports tightly coupled memory configurations.

Co-Simulation uses → 98% 1e

The core was verified using co-simulation against a C++ ISA model.

riscv-dv uses → 99% 1e

The core is verified using Google's RISCV-DV random instruction sequences.

ExactStep uses → 98% 1e

The core is co-simulated against the exactstep C++ ISA model.

FPGA uses → 97% 1e

The core has been exercised on FPGA.

riscv_tcm_top.v ← part of 96% 1e

riscv_tcm_top.v is the top-level file in the riscv repository for the TCM-based core instance.

riscv_top.v ← part of 96% 1e

riscv_top.v is the top-level file in the riscv repository for the cache-based core instance.

RV32IM implements → 99% 1e

The RISC-V CPU core supports RV32IM (integer and multiplication/division extensions).

biRISC-V ← compares with 95% 1e

The README compares the RISC-V CPU core to biRISC-V, noting biRISC-V achieves higher performance.

RISC-V ISA implements → 99% 1e

The core implements the RISC-V ISA base spec v2.1 and privileged ISA spec v1.11.