RV64D Floating-Point Architectural Validation Test Suite

CodeArtifact

An open-source architectural validation test suite from Imperas that targets the ratified RISC-V RV64D extension, which defines 64-bit double-precision floating-point operations conforming to the IEEE 754-2008 arithmetic standard. The suite is part of Imperas' broader Floating-Point test suite family and is used together with the Imperas RISC-V golden reference model in a step-and-compare verification methodology.

First seen 9/24/2026

Last seen 9/24/2026

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Overview

The RV64D Floating-Point Architectural Validation Test Suite is a verification artifact maintained by Imperas Software Ltd. as part of its Imperas RISC-V Verification IP (VIP) solutions. It specifically targets the RV64D extension, which defines 64-bit Double-Precision Floating-Point operations in the ratified RISC-V specification and conforms to the IEEE 754-2008 arithmetic standard.

It is one of three Floating-Point architectural validation suites released by Imperas, alongside the RV32F (32-bit Single-Precision) and RV64F (64-bit Single-Precision) suites. All three are derived from the same underlying methodology and tooling used by Imperas for directed instruction-stream testing.

Scope and Coverage

The RV64D test suite, together with the RV32F and RV64F suites, extends Imperas' earlier range of tests for ratified and near-ratified RISC-V specifications. It is intended to verify that a processor RTL implementation behaves consistently with the Imperas RISC-V golden reference model when executing 64-bit double-precision floating-point instructions defined by the RV64D extension.

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Imperas Floating-Point Architectural Validation Test Suites part of → 86% 1e

The floating-point validation package covers RV64D, indicating the presence of a dedicated RV64D suite.

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Imperas Floating-Point Architectural Validation Test Suites PART_OF Extracted graph relationship

CITATIONS

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[1] The RV64D test suite targets 64-bit Double-Precision Floating-Point (RV64D), conforming to the IEEE 754-2008 arithmetic standard. Imperas Leads The RISC-V Processor Verification Ecosystem - Embedded Computing Design

[2] The RV64D suite is released by Imperas alongside RV32F (32-bit Single-Precision) and RV64F (64-bit Single-Precision) architectural validation test suites, all as open source. Imperas Leads The RISC-V Processor Verification Ecosystem - Embedded Computing Design

[3] The combined Imperas open-source test suites total over 3.5 million instructions and also cover RV32/64IMC, RISC-V Vectors, RV32/64K Crypto, and RV32/64B Bit Manipulation. Imperas Leads The RISC-V Processor Verification Ecosystem - Embedded Computing Design

[4] The suite is used within Imperas' step-and-compare methodology, comparing RTL implementation against the Imperas golden reference model in a SystemVerilog UVM environment, with coverage metrics provided by built-in monitors in the reference model. Imperas Leads The RISC-V Processor Verification Ecosystem - Embedded Computing Design

[5] The Imperas suites are intended for ISA architectural compliance validation and are not comprehensive, complete, full hardware design verification test suites that prove hardware is bug-free. Imperas Leads The RISC-V Processor Verification Ecosystem - Embedded Computing Design

[6] The suite is designed to interoperate with the free riscvOVPsimPlus RISC-V reference model and simulator, which supports ratified RV32/64 IMAFDC plus near-ratified V, H, B, and Crypto (Scalar) extensions. Imperas Leads The RISC-V Processor Verification Ecosystem - Embedded Computing Design