Privileged CSR

Concept

Privileged CSR is represented in the available evidence as a supported verification focus in RISCV-DV, an SV/UVM-based open-source RISC-V instruction generator. RISCV-DV includes both privileged CSR setup randomization and a privileged CSR test suite.

First seen 5/26/2026

Last seen 5/26/2026

Evidence 1 chunks

Wiki v1

WIKI

Overview

In the available evidence, Privileged CSR appears as a verification-related concept within RISCV-DV, an SV/UVM-based open-source instruction generator for RISC-V processor verification. RISCV-DV explicitly lists Privileged CSR setup randomization and a Privileged CSR test suite among its supported features. [C1]

Role in RISCV-DV

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NEIGHBORHOOD

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RELATIONSHIPS

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riscv-dv ← implements 1e

RISCV-DV implements privileged CSR setup randomization.

CITATIONS

3 sources

3 citations — click to collapse

[1] C1: RISCV-DV lists Privileged CSR setup randomization and a Privileged CSR test suite as supported features. chipsalliance/riscv-dv

[2] C2: RISCV-DV is an SV/UVM-based open-source instruction generator for RISC-V processor verification and supports machine mode, supervisor mode, and user mode. chipsalliance/riscv-dv

[3] C3: RISCV-DV lists related verification features including page table randomization and exception support, trap/interrupt handling, MMU stress testing, illegal instruction generation, debug mode support, and co-simulation with multiple ISS implementations. chipsalliance/riscv-dv