Trap and Interrupt Handling

Concept

Trap and interrupt handling is identified as a supported feature of RISCV-DV, an open-source SystemVerilog/UVM instruction generator used for RISC-V processor verification.

First seen 5/26/2026

Last seen 5/26/2026

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WIKI

Overview

Trap and interrupt handling is listed as a supported feature of RISCV-DV, an open-source instruction generator for RISC-V processor verification based on SystemVerilog/UVM. [C1]

Verification context

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RELATIONSHIPS

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riscv-dv ← implements 1e

RISCV-DV implements trap and interrupt handling.

CITATIONS

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[1] C1: RISCV-DV is a SystemVerilog/UVM open-source instruction generator for RISC-V processor verification and lists trap/interrupt handling among its supported features, along with privileged modes and other verification capabilities. chipsalliance/riscv-dv