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Trap and Interrupt Handling

Concept WIKI v1 · 5/26/2026

Trap and interrupt handling is identified as a supported feature of RISCV-DV, an open-source SystemVerilog/UVM instruction generator used for RISC-V processor verification.

Overview

Trap and interrupt handling is listed as a supported feature of RISCV-DV, an open-source instruction generator for RISC-V processor verification based on SystemVerilog/UVM. [C1]

Verification context

RISCV-DV targets RISC-V processor verification and supports machine, supervisor, and user privileged modes. In the same feature set, it includes page-table randomization and exceptions, privileged CSR setup randomization, privileged CSR tests, and trap/interrupt handling. [C1]

Tool support

According to the RISCV-DV project documentation, the generator supports instruction-set configurations RV32IMAFDC and RV64IMAFDC, and it can be used with RTL simulators that support SystemVerilog and UVM 1.2. [C1]

Evidence-limited notes

The provided evidence establishes trap/interrupt handling as a supported RISCV-DV capability, but it does not describe the implementation details, generated handler structure, interrupt sources, trap-vector behavior, or test configuration options.

CITATIONS

1 sources
1 citations
[1] C1: RISCV-DV is a SystemVerilog/UVM open-source instruction generator for RISC-V processor verification and lists trap/interrupt handling among its supported features, along with privileged modes and other verification capabilities. chipsalliance/riscv-dv