Knowledge Base

Concept

In the IBM hardware-verification system described by Naveh et al., a knowledge base is the reusable, maintainable body of hardware-functionality and testing knowledge used by constraint-based random stimuli generators. It is separated from the generic generation engine so that testing knowledge and design-specific models can be reused, adapted to architectural changes, and maintained by specialized knowledge engineers.

First seen 5/26/2026

Last seen 5/26/2026

Evidence 6 chunks

Wiki v1

WIKI

Overview

In the IBM constraint-based random stimuli generation approach for hardware verification, the knowledge base is the maintained body of verification knowledge used by the test-generation tools. The reported technology includes an ontology for describing the functional model and capturing verification expertise, together with a constraint satisfaction problem (CSP) solver. The ontology supports mostly declarative descriptions of hardware functionality and knowledge about testing, while verification scenarios are defined in a separate special-purpose language. The system translates the functional model, expert knowledge, and verification scenarios into constraints that are solved by a dedicated engine.

Within this architecture, the knowledge base is treated as a distinct artifact from the generic generation engine. This separation is important because it allows generic test-generation capabilities and generic testing knowledge to be reused across new hardware designs.

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RELATIONSHIPS

6 connections

Genesys PE ← uses 100% 2e

Genesys PE is built around a knowledge base containing architectural descriptions and expert knowledge.

Expert Knowledge Rules ← part of 100% 2e

The knowledge base contains both architectural descriptions and expert knowledge rules.

Ontology ← part of 90% 2e

The ontology is the primary representation used within the knowledge base.

X-Gen ← uses 100% 1e

X-Gen was designed with a similar knowledge-based architecture as Genesys PE.

Hardware Architecture Validity Rules ← part of 90% 1e

The knowledge base contains the declarative architectural description including validity rules.

Model-based Stimuli Generation ← uses 100% 1e

Model-based stimuli generation is partitioned into a generic engine and a knowledge base input model.

CITATIONS

8 sources

8 citations — click to expand

[1] The IBM random-stimuli generation technology includes an ontology for the functional model and verification expertise, plus a CSP solver. Constraint-Based Random Stimuli Generation for Hardware Verification

[2] The ontology supports mostly declarative descriptions of hardware functionality and testing knowledge, and the system translates models, expertise, and scenarios into constraints. Constraint-Based Random Stimuli Generation for Hardware Verification

[3] The system became a repository of extensive processor-verification knowledge across multiple IBM labs, architectures, and implementations. Constraint-Based Random Stimuli Generation for Hardware Verification

[4] Partitioning the tool into a generic generation engine and a knowledge base enables reuse of generator capabilities and generic testing knowledge for new designs. Constraint-Based Random Stimuli Generation for Hardware Verification

[5] Common design building blocks and common testing knowledge are shared between related hardware designs modeled in a lineage hierarchy. Constraint-Based Random Stimuli Generation for Hardware Verification

[6] Knowledge engineers provide on-site support and adapt the knowledge base to design changes. Constraint-Based Random Stimuli Generation for Hardware Verification

[7] Hardware specification changes must be reflected in the knowledge base and reference model, and separating those modules supports parallel development and correctness checking. Constraint-Based Random Stimuli Generation for Hardware Verification

[8] X-Gen used a similar knowledge-based architecture as Genesys PE and the same CSP solver, with a domain-specific modeling language for system-level concepts. Constraint-Based Random Stimuli Generation for Hardware Verification