Alexandre Joannou
PersonAlexandre Joannou is a researcher at the University of Cambridge (Computer Laboratory) whose work centers on randomized, formal-style testing of RISC-V processor implementations. He is a co-author of the IEEE Design & Test paper introducing TestRIG and Direct Instruction Injection (DII), and a co-author of a 2025 RISC-V Summit Europe presentation extending the TestRIG tool suite.
First seen 5/27/2026
Last seen 8/5/2026
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Overview
Alexandre Joannou is identified in the provided evidence as a researcher affiliated with the University of Cambridge (Computer Laboratory, cl.cam.ac.uk) whose work focuses on randomized verification of RISC-V CPU implementations. He is named as a co-author on two TestRIG-related publications: an IEEE Design & Test paper and a 2025 RISC-V Summit Europe presentation.
Associated work
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3 connectionsAlexandre Joannou is listed as author of the randomized testing paper
Alexandre Joannou is listed as an author of the paper.
TestRIG was authored by Alexandre Joannou among others.
CITATIONS
9 sources9 citations — click to expand
[1] Alexandre Joannou is the first-listed author of 'Randomized Testing of RISC-V CPUs Using Direct Instruction Injection', published in IEEE Design & Test of Computers, 41(1):40-49, February 2024 (DOI: 10.1109/MDAT.2023.3262741). Randomized Testing of RISC-V CPUs Using Direct Instruction Injection - researchr publication record
[2] Co-authors on the IEEE Design & Test paper are Peter Rugg, Jonathan Woodruff, Franz A. Fuchs, Marno van der Maas, Matthew Naylor, Michael Roe, Robert N. M. Watson, Peter G. Neumann, and Simon W. Moore. Randomized Testing of RISC-V CPUs using Direct Instruction Injection (IEEE Design & Test 2023/2024 preprint)
[3] TestRIG (Testing with Random Instruction Generation) is a testing framework that checks equivalence between a model and an implementation by generating random instruction sequences, executing them on both, and comparing execution traces; this tandem-execution approach does not prove equivalence but can demonstrate divergence. Randomized Testing of RISC-V CPUs using Direct Instruction Injection (IEEE Design & Test preprint)
[4] TestRIG uses the RISC-V Formal Interface (RVFI) standard to observe state changes after each instruction, and uses Direct Instruction Injection (DII) where the next instruction is supplied by the test harness regardless of the CPU's program counter. Randomized Testing of RISC-V CPUs using Direct Instruction Injection (IEEE Design & Test preprint)
[5] The authors report that TestRIG was used to test many standard RISC-V extensions and the experimental CHERI security extension, gave more thorough coverage than developer-written unit tests, and was effective at detecting issues in instruction semantics, the pipeline, and data caches, completely replacing instruction-set level unit testing for development. Randomized Testing of RISC-V CPUs using Direct Instruction Injection (IEEE Design & Test preprint)
[6] Joannou is a co-author of 'Who tests the TestRIG? Tooling for randomised tandem verification' presented at RISC-V Summit Europe 2025, alongside Peter Rugg, Jonathan Woodruff, Franz A. Fuchs, and Simon W. Moore, all of the University of Cambridge. Who tests the TestRIG? Tooling for randomised tandem verification (RISC-V Summit Europe 2025 abstract)
[7] The 2025 presentation describes TestRIG as an ecosystem for cross-verifying RISC-V implementations using a standard RVFI-DII interface, with QuickCheckVEngine using Haskell's QuickCheck to generate tests and shrink divergences, comparing implementations against the RISC-V Sail golden model. Who tests the TestRIG? Tooling for randomised tandem verification (RISC-V Summit Europe 2025 abstract)
[8] TestRIG is in use to test CHERI in the Toooba and CVA6 processors, and has community engagement with users and contributors from Microsoft Research, lowRISC, and SCI Semiconductor. Who tests the TestRIG? Tooling for randomised tandem verification (RISC-V Summit Europe 2025 abstract)
[9] TestRIG was first presented at the RISC-V Summit in Zurich in 2019, and the 2025 presentation discusses improvements including mutation-based coverage tooling, static test suite generation features, and a single-implementation fuzzing mode, motivated by testing the Toooba processor including the CHERI security extensions. Who tests the TestRIG? Tooling for randomised tandem verification (RISC-V Summit Europe 2025 abstract)