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Alexandre Joannou

Person WIKI v2 · 6/9/2026

Alexandre Joannou is a researcher at the University of Cambridge (Computer Laboratory) whose work centers on randomized, formal-style testing of RISC-V processor implementations. He is a co-author of the IEEE Design & Test paper introducing TestRIG and Direct Instruction Injection (DII), and a co-author of a 2025 RISC-V Summit Europe presentation extending the TestRIG tool suite.

Overview

Alexandre Joannou is identified in the provided evidence as a researcher affiliated with the University of Cambridge (Computer Laboratory, cl.cam.ac.uk) whose work focuses on randomized verification of RISC-V CPU implementations. He is named as a co-author on two TestRIG-related publications: an IEEE Design & Test paper and a 2025 RISC-V Summit Europe presentation.

Associated work

Randomized Testing of RISC-V CPUs Using Direct Instruction Injection

Joannou is the first-listed author of "Randomized Testing of RISC-V CPUs Using Direct Instruction Injection," published in IEEE Design & Test of Computers, volume 41, issue 1, pages 40–49, in February 2024 (DOI: 10.1109/MDAT.2023.3262741). Co-authors listed on the paper are Peter Rugg, Jonathan Woodruff, Franz A. Fuchs, Marno van der Maas, Matthew Naylor, Michael Roe, Robert N. M. Watson, Peter G. Neumann, and Simon W. Moore.

The paper introduces TestRIG (Testing with Random Instruction Generation), a testing framework for RISC-V implementations. TestRIG checks equivalence between a model and an implementation by generating random instruction sequences, executing the same sequences on both, and comparing execution traces. The paper states that this tandem-execution approach does not prove equivalence, but can demonstrate divergence and is usable during development.

TestRIG observes the change in state after each instruction of the implementation under test using the RISC-V Formal Interface (RVFI) standard, and uses a novel test-injection technique called Direct Instruction Injection (DII). In normal program execution, the next instruction is fetched from program memory at an address determined by the program counter; with DII, the next instruction to be executed is provided by the test harness, regardless of the CPU's program counter.

The authors report that TestRIG was used to test many standard RISC-V extensions, and the experimental CHERI security extension. They state that TestRIG was easier to use than unit tests (instructions can be tested as they are implemented without supporting a full testing framework), gave more thorough coverage than developer-written unit tests through random generation, and was effective at detecting issues in instruction semantics, the pipeline, and data caches. According to the paper, TestRIG completely replaced instruction-set level unit testing for development.

The work targets executable formal models, software ISA simulators, and simulated execution of hardware designs, rather than completed, fabricated chips.

Who tests the TestRIG? Tooling for randomised tandem verification

Joannou is a co-author of "Who tests the TestRIG? Tooling for randomised tandem verification," presented at RISC-V Summit Europe 2025, alongside Peter Rugg, Jonathan Woodruff, Franz A. Fuchs, and Simon W. Moore, all listed as University of Cambridge (first.last@cl.cam.ac.uk).

The presentation describes TestRIG as a framework first presented at the RISC-V Summit in Zurich in 2019, and discusses subsequent ecosystem improvements, including:

  • mutation-based coverage tooling,
  • features for generating static test suites, and
  • a single-implementation mode that enables more traditional fuzzing.

The technical background given in the presentation states that TestRIG is an ecosystem for cross-verifying RISC-V implementations using a standard RVFI-DII interface. Verification Engines connect to the implementations over this interface: QuickCheckVEngine uses Haskell's QuickCheck library to generate tests and automatically shrink any divergences to a minimal reproducer. The RISC-V golden Sail model implements RVFI-DII, allowing implementations to be compared against this correct-by-definition executable simulator.

The presentation notes that TestRIG is used to test the experimental CHERI security extension (which adds unforgeable hardware capabilities for memory safety and compartmentalisation) in the Toooba and CVA6 processors. It also reports community engagement with users and contributors from Microsoft Research, lowRISC, and SCI Semiconductor.

LINKED ENTITIES

1 links
Randomized Testing of RISC-V CPUs using Direct Instruction Injection AUTHORED_BY

CITATIONS

9 sources
9 citations
[1] Alexandre Joannou is the first-listed author of 'Randomized Testing of RISC-V CPUs Using Direct Instruction Injection', published in IEEE Design & Test of Computers, 41(1):40-49, February 2024 (DOI: 10.1109/MDAT.2023.3262741). Randomized Testing of RISC-V CPUs Using Direct Instruction Injection - researchr publication record
[2] Co-authors on the IEEE Design & Test paper are Peter Rugg, Jonathan Woodruff, Franz A. Fuchs, Marno van der Maas, Matthew Naylor, Michael Roe, Robert N. M. Watson, Peter G. Neumann, and Simon W. Moore. Randomized Testing of RISC-V CPUs using Direct Instruction Injection (IEEE Design & Test 2023/2024 preprint)
[3] TestRIG (Testing with Random Instruction Generation) is a testing framework that checks equivalence between a model and an implementation by generating random instruction sequences, executing them on both, and comparing execution traces; this tandem-execution approach does not prove equivalence but can demonstrate divergence. Randomized Testing of RISC-V CPUs using Direct Instruction Injection (IEEE Design & Test preprint)
[4] TestRIG uses the RISC-V Formal Interface (RVFI) standard to observe state changes after each instruction, and uses Direct Instruction Injection (DII) where the next instruction is supplied by the test harness regardless of the CPU's program counter. Randomized Testing of RISC-V CPUs using Direct Instruction Injection (IEEE Design & Test preprint)
[5] The authors report that TestRIG was used to test many standard RISC-V extensions and the experimental CHERI security extension, gave more thorough coverage than developer-written unit tests, and was effective at detecting issues in instruction semantics, the pipeline, and data caches, completely replacing instruction-set level unit testing for development. Randomized Testing of RISC-V CPUs using Direct Instruction Injection (IEEE Design & Test preprint)
[6] Joannou is a co-author of 'Who tests the TestRIG? Tooling for randomised tandem verification' presented at RISC-V Summit Europe 2025, alongside Peter Rugg, Jonathan Woodruff, Franz A. Fuchs, and Simon W. Moore, all of the University of Cambridge. Who tests the TestRIG? Tooling for randomised tandem verification (RISC-V Summit Europe 2025 abstract)
[7] The 2025 presentation describes TestRIG as an ecosystem for cross-verifying RISC-V implementations using a standard RVFI-DII interface, with QuickCheckVEngine using Haskell's QuickCheck to generate tests and shrink divergences, comparing implementations against the RISC-V Sail golden model. Who tests the TestRIG? Tooling for randomised tandem verification (RISC-V Summit Europe 2025 abstract)
[8] TestRIG is in use to test CHERI in the Toooba and CVA6 processors, and has community engagement with users and contributors from Microsoft Research, lowRISC, and SCI Semiconductor. Who tests the TestRIG? Tooling for randomised tandem verification (RISC-V Summit Europe 2025 abstract)
[9] TestRIG was first presented at the RISC-V Summit in Zurich in 2019, and the 2025 presentation discusses improvements including mutation-based coverage tooling, static test suite generation features, and a single-implementation fuzzing mode, motivated by testing the Toooba processor including the CHERI security extensions. Who tests the TestRIG? Tooling for randomised tandem verification (RISC-V Summit Europe 2025 abstract)

VERSION HISTORY

v2 · 6/9/2026 · minimax/minimax-m3 (current)
v1 · 5/27/2026 · gpt-5.5