Addressing Mode (SAM24/SAM31/SAM64)

Concept

In the IBM z/Architecture, the Addressing Mode is a machine state that controls the number of bits used to form effective addresses for instruction and operand references. It is set by the simple instructions SAM24, SAM31, and SAM64, which switch the processor to 24-bit, 31-bit, or 64-bit addressing, respectively.

First seen 8/5/2026

Last seen 8/5/2026

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Overview

In the IBM z/Architecture, the Addressing Mode is a processor state that determines how many bits of an address are used when forming effective addresses for instructions and data. Three simple instructions, SAM24, SAM31, and SAM64, are used to set this state to 24-bit, 31-bit, or 64-bit addressing, respectively.

Role in Instruction Set and Hazards

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Machine State Detection and Restoration Mechanism ← uses 90% 1e

The Machine State Detection and Restoration Mechanism must handle addressing mode changes such as SAM24/SAM31/SAM64 in IBM z/Architecture.

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CITATIONS

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[1] SAM24, SAM31 and SAM64 are simple instructions in IBM z/Architecture that set the Addressing Mode to 24-bit, 31-bit, or 64-bit addressing, respectively. IMPLEMENTING RANDOM CONTENT OF PROGRAM LOOPS IN RANDOM TEST GENERATION FOR PROCESSOR VERIFICATION - Patent application

[2] Addressing Mode is an example of an "instruction and data translation hazard" — a hardware state that is difficult to save and restore. IMPLEMENTING RANDOM CONTENT OF PROGRAM LOOPS IN RANDOM TEST GENERATION FOR PROCESSOR VERIFICATION - Patent application

[3] A randomly generated SAM31 instruction after a branch to an address below 0x000000007FFFFFFF in a loop that originally used 64-bit addresses greater than 0x000000007FFFFFFF can leave the processor in a state where a simple branch back to the loop start is logically impossible. IMPLEMENTING RANDOM CONTENT OF PROGRAM LOOPS IN RANDOM TEST GENERATION FOR PROCESSOR VERIFICATION - Patent application

[4] The Machine State Detection and Restoration Mechanism aids successful generation of loops that remember the state at the top of the loop and restore it at each end point if there is a difference. IMPLEMENTING RANDOM CONTENT OF PROGRAM LOOPS IN RANDOM TEST GENERATION FOR PROCESSOR VERIFICATION - Patent application

[5] Rare hazards that are difficult to save and restore can be avoided by adding instructions that alter that state to the global class restrictions. IMPLEMENTING RANDOM CONTENT OF PROGRAM LOOPS IN RANDOM TEST GENERATION FOR PROCESSOR VERIFICATION - Patent application