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Addressing Mode (SAM24/SAM31/SAM64)

Concept WIKI v1 · 8/5/2026

In the IBM z/Architecture, the Addressing Mode is a machine state that controls the number of bits used to form effective addresses for instruction and operand references. It is set by the simple instructions SAM24, SAM31, and SAM64, which switch the processor to 24-bit, 31-bit, or 64-bit addressing, respectively.

Overview

In the IBM z/Architecture, the Addressing Mode is a processor state that determines how many bits of an address are used when forming effective addresses for instructions and data. Three simple instructions, SAM24, SAM31, and SAM64, are used to set this state to 24-bit, 31-bit, or 64-bit addressing, respectively.

Role in Instruction Set and Hazards

The Addressing Mode is one of several machine-level states that can be altered during program execution. When a random or unconstrained code generator (such as a constrained-random test generator for processor verification) emits a branch or addressing-mode-changing instruction in the middle of a loop, the processor may end up in a state from which a simple branch back to the loop start is logically impossible. The Addressing Mode therefore qualifies as an "instruction and data translation hazard" — a state that is difficult to save and restore, and which test-generation logic must accommodate or constrain.

Worked Example from z/Architecture

  • A loop begins in 64-bit addressing mode and uses addresses greater than 0x000000007FFFFFFF.
  • A randomly generated branch inside the loop body targets an instruction address below 0x000000007FFFFFFF.
  • A subsequent randomly generated SAM31 instruction puts the processor into 31-bit addressing mode.
  • At this point a simple branch back to the start of the loop is no longer logically possible because the destination address in the loop is only addressable in 64-bit mode. Test generation therefore fails.

This example illustrates why rare hardware states such as the Addressing Mode must be either fully restorable by the surrounding generation mechanism, or constrained away by adding state-changing instructions (e.g., SAM24/SAM31/SAM64) to the global class restrictions.

Use by Verification Tooling

The Addressing Mode is specifically cited as a state that benefits from a Machine State Detection and Restoration Mechanism during constrained-random test generation for processor verification. By detecting the state at the top of a loop and restoring it at every loop end point, such a mechanism allows loops to be re-entered correctly even when addressing-mode changes have occurred in the loop body.

Related IBM Reference

The behavior of SAM24, SAM31, and SAM64 is defined in the IBM publication z/Architecture Principles of Operation.

LINKED ENTITIES

1 links
Machine State Detection and Restoration Mechanism USES

CITATIONS

5 sources
5 citations
[1] SAM24, SAM31 and SAM64 are simple instructions in IBM z/Architecture that set the Addressing Mode to 24-bit, 31-bit, or 64-bit addressing, respectively. IMPLEMENTING RANDOM CONTENT OF PROGRAM LOOPS IN RANDOM TEST GENERATION FOR PROCESSOR VERIFICATION - Patent application
[2] Addressing Mode is an example of an "instruction and data translation hazard" — a hardware state that is difficult to save and restore. IMPLEMENTING RANDOM CONTENT OF PROGRAM LOOPS IN RANDOM TEST GENERATION FOR PROCESSOR VERIFICATION - Patent application
[3] A randomly generated SAM31 instruction after a branch to an address below 0x000000007FFFFFFF in a loop that originally used 64-bit addresses greater than 0x000000007FFFFFFF can leave the processor in a state where a simple branch back to the loop start is logically impossible. IMPLEMENTING RANDOM CONTENT OF PROGRAM LOOPS IN RANDOM TEST GENERATION FOR PROCESSOR VERIFICATION - Patent application
[4] The Machine State Detection and Restoration Mechanism aids successful generation of loops that remember the state at the top of the loop and restore it at each end point if there is a difference. IMPLEMENTING RANDOM CONTENT OF PROGRAM LOOPS IN RANDOM TEST GENERATION FOR PROCESSOR VERIFICATION - Patent application
[5] Rare hazards that are difficult to save and restore can be avoided by adding instructions that alter that state to the global class restrictions. IMPLEMENTING RANDOM CONTENT OF PROGRAM LOOPS IN RANDOM TEST GENERATION FOR PROCESSOR VERIFICATION - Patent application