Arithmetic Logic Unit (ALU)

Concept

An Arithmetic Logic Unit (ALU) is a processor execution unit that performs arithmetic and logical operations. In the provided evidence, it appears both as a core component of the OR1200/OpenRISC1200 processor and as a standalone verification benchmark, including a reduced 8-function variant. The evidence also covers specialized ALU designs in reversible logic and fully homomorphic encryption.

First seen 8/6/2026

Last seen 8/13/2026

Evidence 5 chunks

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Arithmetic Logic Unit (ALU)

Overview

An Arithmetic Logic Unit (ALU) performs arithmetic and logical operations on input data. In the verification literature provided here, the operation to be performed can be selected through an input such as op; for example, a scenario may force op = add to trigger an addition. Separately, reversible-logic research describes the ALU as the "prime performing unit" in a computing device and motivates making it fault tolerant.

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NEIGHBORHOOD

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RELATIONSHIPS

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OpenRISC1200 (OR1200) part of → 100% 1e

The OR1200 core includes an ALU as one of its execution units.

RISC processor part of → 95% 1e

The RISC processor contains an ALU as one of its components.

ALU Reduced ← derived from 85% 1e

The ALU reduced is an alternative CPU with a reduced ALU implementing fewer functions.

LINKED ENTITIES

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OpenRISC1200 (OR1200) PART_OF Extracted graph relationship

CITATIONS

8 sources

8 citations — click to expand

[1] An ALU operation can be selected by an input such as `op`, and a scenario may force `op = add` to make the ALU perform addition on its data inputs. Minimal Stimuli Generation in Simulation-based Verification

[2] The OR1200 core includes three execution units: the load/store unit (LSU), the arithmetic logic unit (ALU), and the MAC unit. Verifying Open Source CPU Cores using Instruction Set Simulators in OVM Environments

[3] The OR1200 core is a 32-bit scalar RISC core with a Harvard memory architecture and a single-issue 5-stage integer pipeline. Verifying Open Source CPU Cores using Instruction Set Simulators in OVM Environments

[4] A Harvard-architecture RISC benchmark used in minimal-stimuli experiments is composed of typical components including a control unit, program counter, ALU, external data memory, and a stack pointer. Minimal Stimuli Generation in Simulation-based Verification

[5] The benchmark suite includes an alternative CPU component called 'ALU reduced' that implements 8 ALU functions. Minimal Stimuli Generation in Simulation-based Verification

[6] In the benchmark results, ALU reduced used 8 scenarios and ALU used 16 scenarios; for tS = 1 the reported counts were 42/8/8 for ALU reduced and 47/16/time out for ALU, and for tS = 40 they were 428/320/320 for ALU reduced and 989/640/time out for ALU. Minimal Stimuli Generation in Simulation-based Verification

[7] Reversible-logic research describes the ALU as the prime performing unit in a computing device and presents a fault-tolerant reversible ALU using parity-preserving reversible logic gates that can generate up to seven arithmetic operations and four logical operations. Design of Parity Preserving Logic Based Fault Tolerant Reversible Arithmetic Logic Unit

[8] The ComputeFHE library includes an optimized ALU architecture using FHE-friendly logic primitives and reports up to 3.9x performance improvement for selected operations by reducing required bootstrapping operations. ComputeFHE: A Privacy-Preserving General-Purpose Computation Library