Arithmetic Logic Unit (ALU)

Overview

An Arithmetic Logic Unit (ALU) performs arithmetic and logical operations on input data. In the verification literature provided here, the operation to be performed can be selected through an input such as op; for example, a scenario may force op = add to trigger an addition. Separately, reversible-logic research describes the ALU as the "prime performing unit" in a computing device and motivates making it fault tolerant.

ALU as a processor component

In the OR1200 core, the ALU is one of the processor's execution units, alongside the load/store unit (LSU) and the MAC unit. The surrounding processor context is a 32-bit scalar RISC core with a Harvard memory architecture and a single-issue 5-stage integer pipeline.

A separate verification benchmark paper also models a Harvard-architecture RISC processor as being composed of typical components including a control unit, program counter, ALU, external data memory, and a stack pointer. In that setting, the ALU is treated both as a normal processor component and as an individual design-under-verification (DUV).

Use in simulation-based verification

The ALU appears directly in scenario-based verification. A scenario is defined as a Boolean function over design signals, and ALU-specific scenarios can constrain the selected operation. One explicit example is a scenario that forces op = add.

The same source highlights why ALU scenarios matter in constrained-random verification: a single stimulus can trigger multiple scenarios at once. For example, an ALU addition may coincide with a program-counter increment, which can reduce the number of required stimuli when building a sufficient regression set.

Reduced ALU benchmark

The benchmark suite includes an "ALU reduced" design, described as an alternative CPU component implementing 8 ALU functions. This reduced version is used as a simpler benchmark alongside a fuller ALU benchmark.

In the reported experiments:

• ALU reduced used 8 scenarios.
• ALU used 16 scenarios.

For threshold tS = 1, the reported stimulus counts were:

For threshold tS = 40, the reported stimulus counts were:

These results show that the reduced ALU was easier to handle in the minimal-stimuli experiments than the fuller ALU benchmark.

Specialized ALU research

Fault-tolerant reversible ALU

One cited research effort designs a fault-tolerant reversible ALU using parity-preserving reversible logic gates. The design is reported to support up to seven arithmetic operations and four logical operations.

ALU architecture for FHE

In fully homomorphic encryption (FHE), the cited ComputeFHE library includes an optimized ALU architecture built around FHE-friendly logic primitives. The paper reports reductions in required bootstrapping operations, with up to 3.9× performance improvement for selected operations.