ALU Reduced

Concept

ALU reduced is a simplified variant of an Arithmetic Logic Unit (ALU) used as a design under verification (DUV) benchmark in simulation-based verification research. It implements 8 ALU functions, in contrast to the full ALU benchmark which implements 16 functions, and is used to evaluate minimal stimuli generation techniques.

First seen 8/6/2026

Last seen 8/6/2026

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ALU Reduced

Definition

ALU reduced is a reduced (simplified) variant of an Arithmetic Logic Unit (ALU) that is used as a benchmark design in simulation-based functional verification. It is described in the context of minimal stimuli generation, where it serves as one of several design under verification (DUV) examples used to evaluate the efficiency of different stimulus generation approaches.

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Arithmetic Logic Unit (ALU) derived from → 85% 1e

The ALU reduced is an alternative CPU with a reduced ALU implementing fewer functions.

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Arithmetic Logic Unit (ALU) DERIVED_FROM Extracted graph relationship

CITATIONS

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[1] ALU reduced implements 8 ALU functions, described as a CPU with a reduced ALU. Minimal Stimuli Generation in Simulation-based Verification

[2] ALU reduced is evaluated with 8 scenarios and benchmarked across naive, iterative, and minimal stimulus generation approaches in Table I (run times 0.04s, 0.02s, 0.16s respectively). Minimal Stimuli Generation in Simulation-based Verification

[3] In Table II with threshold tS = 40, ALU reduced is evaluated across naive (428 stimuli, 0.08s), iterative (320 stimuli, 0.10s), and minimal (320 stimuli, 0.21s) approaches. Minimal Stimuli Generation in Simulation-based Verification