ARM V4 ISA

Concept

ARM V4 is an instruction set architecture (ISA) for which an embedded processor model, ARMChisel, is constructed using the Chisel hardware description language. A random instruction generator designed to cover the full ARM V4 ISA is used as a test stimulus source to support functional verification of the ARMChisel processor model.

First seen 8/6/2026

Last seen 8/6/2026

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ARM V4 ISA

The ARM V4 instruction set architecture (ISA) is the target ISA of an embedded processor model referred to as ARMChisel, which is built using the Chisel hardware construction language. The ARMChisel model is described as a highly complex hardware design whose functional verification was investigated in published research on processor model validation built by Chisel.

Verification context

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RELATIONSHIPS

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ARMChisel ← implements 100% 1e

ARMChisel is a processor model compatible with the ARM V4 ISA.

Random Instruction Generator ← uses 100% 1e

The random instruction generator supports all instructions of the ARM V4 ISA architecture.

LINKED ENTITIES

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ARMChisel IMPLEMENTS Extracted graph relationship

Random Instruction Generator USES Extracted graph relationship

CITATIONS

5 sources

5 citations — click to expand

[1] ARMChisel is a processor model built with Chisel that is compatible with the ARM V4 ISA and serves as the design under test in the cited verification research. Research on functional verification method processor model built by Chisel | Xibei Gongye Daxue Xuebao/Journal of Northwestern Polytechnical University

[2] A random instruction generator was designed to support all instructions of the ARM V4 ISA architecture in order to speed up generation of test stimuli. Research on functional verification method processor model built by Chisel | Xibei Gongye Daxue Xuebao/Journal of Northwestern Polytechnical University

[3] Four verification stages were defined for the Chisel-based processor model: primary verification at the Chisel level, rapid coverage verification, direct test verification, and verification of complex applications. Research on functional verification method processor model built by Chisel | Xibei Gongye Daxue Xuebao/Journal of Northwestern Polytechnical University

[4] Testbenches were built in both the Chisel environment and the Verilog environment around the embedded processor model, with coverage collection and error detection/localization. Research on functional verification method processor model built by Chisel | Xibei Gongye Daxue Xuebao/Journal of Northwestern Polytechnical University

[5] FPGA-based acceleration was used to speed up verification of large-scale application programs and shorten the verification cycle. Research on functional verification method processor model built by Chisel | Xibei Gongye Daxue Xuebao/Journal of Northwestern Polytechnical University