ARM V4 ISA

The ARM V4 instruction set architecture (ISA) is the target ISA of an embedded processor model referred to as ARMChisel, which is built using the Chisel hardware construction language. The ARMChisel model is described as a highly complex hardware design whose functional verification was investigated in published research on processor model validation built by Chisel.

Verification context

The published study treats an ARM Chisel processor model, compatible with the ARM V4 ISA, as the design under test (DUT) for functional verification research. The work focuses on:

• Designing a random instruction generator that supports all instructions of the ARM V4 ISA architecture, in order to increase the speed of generating test stimuli.
• Defining four verification stages tailored to the Chisel-based processor model: primary verification at the Chisel level, rapid coverage verification, direct test verification, and verification of complex applications, with the goal of achieving expected coverage.
• Building testbenches in both the Chisel environment and the Verilog environment on top of the embedded processor model, capable of collecting coverage while quickly and accurately detecting and localizing errors.
• Using FPGA-based acceleration to speed up verification of large-scale application programs and shorten the verification cycle.

Role in the ARMChisel ecosystem

The ARM V4 ISA defines the instruction space that ARMChisel implements and that the random instruction generator must exhaustively cover when producing randomized test stimuli for the DUT.

Related entities

• ARMChisel — a Chisel-based processor model that implements the ARM V4 ISA and serves as the design under test in the cited verification research.
• Random Instruction Generator — a verification technique that targets the ARM V4 ISA by generating randomized instructions across the full ISA to drive functional verification of ARMChisel.