design under verification (DUV)

Concept

In the provided evidence, a design under verification (DUV) is the target design being simulated in a simulation-based processor-verification flow. Stimuli are generated and applied to the processor inputs, functional coverage is monitored, and coverage feedback from the DUV simulation can be used to adjust stimulus-generation constraints.

First seen 5/26/2026

Last seen 5/26/2026

Evidence 2 chunks

Wiki v1

WIKI

Overview

A design under verification (DUV) is the design being exercised by a verification process. In the cited processor-verification work, the DUV appears in a simulation-based flow where generated stimuli are applied to processor inputs and the resulting functional coverage is monitored to assess verification completeness. [C1]

Role in simulation-based processor verification

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CITATIONS

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4 citations — click to collapse

[1] C1: In simulation-based processor verification, stimuli are generated with pseudorandom generators, applied to processor inputs, and coverage of processor functionality is monitored to determine verification completeness. Automation of Processor Verification Using Recurrent Neural Networks

[2] C2: Stimuli in the described flow can be represented as bit vectors applied to processor input ports or as programs loaded directly into program memory. Automation of Processor Verification Using Recurrent Neural Networks

[3] C3: The cited technique dynamically alters PRG constraints using a recurrent neural network that receives coverage feedback from simulation of the design under verification. Automation of Processor Verification Using Recurrent Neural Networks

[4] C4: The cited experiments used Codasip processors for demonstration and reported faster coverage closure plus identification of a small high-coverage stimulus set usable for regression tests. Automation of Processor Verification Using Recurrent Neural Networks