Overview
A design under verification (DUV) is the design being exercised by a verification process. In the cited processor-verification work, the DUV appears in a simulation-based flow where generated stimuli are applied to processor inputs and the resulting functional coverage is monitored to assess verification completeness. [C1]
Role in simulation-based processor verification
The evidence describes a verification loop with three main elements:
- Stimulus generation — stimuli are generated using pseudorandom generators (PRGs). [C1]
- Application to the DUV — generated stimuli are applied to the processor inputs; stimuli may be bit vectors on input ports or programs loaded into program memory. [C2]
- Coverage monitoring — achieved coverage of the processor functionality is monitored to determine verification completeness. [C1]
Coverage-feedback use
The cited work proposes dynamically altering PRG constraints using a recurrent neural network. The recurrent neural network receives coverage feedback from the simulation of the design under verification, and this feedback is used to influence subsequent stimulus generation. [C3]
Example context from the evidence
For demonstration, the cited study used processors provided by Codasip because their coverage state spaces were reasonably large and varied across processor kinds. The reported experimental outcome was faster coverage closure and the isolation of a small set of high-coverage stimuli suitable for regression tests. [C4]