chipsalliance

Organization

chipsalliance is evidenced as the GitHub owner namespace for `chipsalliance/riscv-dv`, an open-source SV/UVM-based random instruction generator for RISC-V processor verification that the supplied sources associate with CHIPS Alliance.

First seen 5/24/2026

Last seen 9/5/2026

Evidence 25 chunks

Wiki v3

WIKI

chipsalliance

Overview

chipsalliance is evidenced in the supplied GitHub metadata as the owner login and namespace for the public repository chipsalliance/riscv-dv. The metadata identifies repository ID 167140400, repository name-with-owner chipsalliance/riscv-dv, and Git import URL https://github.com/chipsalliance/riscv-dv.git.[C1]

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NEIGHBORHOOD

4 nodes · 5 edges

graph · chipsalliance · depth=1

RELATIONSHIPS

10 connections

riscv-dv ← published by 100% 6e

RISCV-DV was originally developed by Google and is now maintained by the CHIPS Alliance.

Rocket ← published by 100% 2e

Rocket Chip is published by CHIPS Alliance on GitHub.

RISC-V Vector Tests Generator ← published by 100% 2e

The RISC-V Vector Tests Generator is provided by the CHIPS Alliance.

riscv-dv ← authored by 97% 2e

riscv-dv is authored and maintained by CHIPS Alliance as an open-source project.

riscv-dv introduces → 100% 2e

CHIPS Alliance developed and open-sourced the riscv-dv random instruction generator.

Antmicro ← part of 80% 1e

Antmicro works with CHIPS Alliance on the Caliptra Root of Trust project

VeeR EL2 ← published by 98% 1e

VeeR EL2 is hosted by CHIPS Alliance.

Custom GitHub Actions Runners introduces → 90% 1e

Custom GitHub Actions Runners were developed within the CHIPS Alliance.

Caliptra Root of Trust ← part of 1e

Caliptra Root of Trust is a project that is part of CHIPS Alliance.

force-riscv ← published by 70% 1e

FORCE-RISCV is published by the OpenHW Group, which is part of CHIPS Alliance.

CITATIONS

7 sources

7 citations — click to expand

[1] GitHub metadata identifies `chipsalliance` as the owner login for the public repository `chipsalliance/riscv-dv`, repository ID `167140400`, and Git URL `https://github.com/chipsalliance/riscv-dv.git`; it also identifies the source-file page for `src/riscv_instr_sequence.sv`. riscv-dv/src/riscv_instr_sequence.sv at master · chipsalliance/riscv-dv

[2] The `riscv-dv` README describes RISCV-DV as a SystemVerilog/UVM-based open-source instruction generator for RISC-V processor verification and lists its supported verification features. chipsalliance/riscv-dv

[3] The Design & Reuse article states that CHIPS Alliance developed an open-source `riscv-dv` random instruction generator for RISC-V processor verification and describes `riscv_asm_program_gen.sv` as generating complete RISC-V assembly programs. RISC-V source class riscv_asm_program_gen, the brain behind ...

[4] The Design & Reuse article states that `riscv_instr_gen_config` is randomized from `riscv_instr_base_test.sv` and controls settings such as RISC-V extension, privilege mode, instruction counts, and generation of `ebreak`, `dret`, `fence`, and `wfi` instructions. RISC-V source class riscv_asm_program_gen, the brain behind ...

[5] The Design & Reuse article describes `gen_program()` as the main function for generating program sections and lists related calls including directed-instruction stream selection, header generation, GPR initialization, instruction-stream conversion, and subprogram insertion. RISC-V source class riscv_asm_program_gen, the brain behind ...

[6] The `riscv-dv` README states that running the generator requires an RTL simulator supporting SystemVerilog and UVM 1.2 and says the generator has been verified with Synopsys VCS, Cadence Incisive/Xcelium, Mentor Questa, and Aldec Riviera-PRO. chipsalliance/riscv-dv

[7] The `riscv-dv` README states that RISC-V DV has been contributed to CHIPS Alliance, that regular meetings are held for issues and development progress, and that the project is not an officially supported Google product. chipsalliance/riscv-dv