2026-08-08
2 items 65 entities 72 connections
Processed 50 entities and 59 relations.
Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing Niklas Bruns Vladimir Herdt Daniel Große Rolf Drechsler University of Bremen DFKI GmbH Johannes Kepler University Linz Coverage-Guided Fuzzing Cross-Level Processor Verification RTL Processor Verification Co-Simulation Instruction Set Architecture Mutation-Based Test Generation Processor-Level Input Stimuli Generation AFL LLVM libFuzzer RISC-V VexRiscv RISC-V VP Instruction Set Simulator Translation Buffer Execution Controller Fast Exploration Mutation Enhanced Havoc Mutation Test Vector Clustering Post-Processing Virtual Coverage Edge Coverage Register Value Comparison Verilator SystemC TLM SpinalHDL Constraint Satisfaction Problem Model-Based Test Generation Symbolic Execution Bitflip Mutation Arithmetic Mutation Havoc Mutation CSR Testing RV32IM Infinite Loop Prevention RFUZZ SpinalFuzz RISCV-DV RISC-V Torture Test Generator Genesys-Pro Bayesian Network Test Generation FPGA Acceleration for Fuzzing Mann-Whitney U Test Endless Instruction Stream Generation
Processed 15 entities and 13 relations.