Niklas Bruns

Person

Niklas Bruns is a researcher affiliated in the cited paper metadata with the Institute of Computer Science at the University of Bremen. He is listed as an author of work on cross-level RTL processor verification using randomized, coverage-guided instruction stream generation, ISS-based co-simulation, and Coverage-guided Aging.

First seen 5/25/2026

Last seen 6/5/2026

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Overview

Niklas Bruns is listed as an author of "Cross-Level Processor Verification via Endless Randomized Instruction Stream Generation with Coverage-guided Aging", together with Vladimir Herdt, Eyck Jentzsch, and Rolf Drechsler. The paper metadata places Bruns at the Institute of Computer Science, University of Bremen, Bremen, Germany, and gives the contact address nbruns@uni-bremen.de. [C1]

Research context

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Cross-level processor verification via endless randomized instruction stream generation with coverage-guided aging ← authored by 100% 6e

Niklas Bruns is listed as an author of the paper.

University of Bremen part of → 100% 3e

Niklas Bruns is affiliated with the University of Bremen.

Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing ← authored by 100% 2e

Niklas Bruns is listed as an author of the paper.

LINKED ENTITIES

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Cross-level processor verification via endless randomized instruction stream generation with coverage-guided aging AUTHORED_BY Extracted graph relationship

University of Bremen PART_OF Extracted graph relationship

CITATIONS

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5 citations — click to expand

[1] Niklas Bruns is listed as an author of the paper 'Cross-Level Processor Verification via Endless Randomized Instruction Stream Generation with Coverage-guided Aging' and is affiliated in the metadata with the Institute of Computer Science, University of Bremen. Cross-Level Processor Verification via Endless Randomized Instruction Stream Generation with Coverage-guided Aging

[2] The cross-level processor verification paper proposes a randomized coverage-guided endless instruction stream generator, uses an ISS in tight co-simulation, updates coverage from ISS execution state, and applies Coverage-guided Aging. Cross-Level Processor Verification via Endless Randomized Instruction Stream Generation with Coverage-guided Aging

[3] The cross-level processor verification paper reports a case study with an industrial pipelined 32-bit RISC-V processor and states that the approach demonstrates effectiveness for finding intricate corner-case bugs. Cross-Level Processor Verification via Endless Randomized Instruction Stream Generation with Coverage-guided Aging

[4] The coverage-guided fuzzing work reports finding 24 bugs in the VexRiscv RTL core and states that coverage-guided fuzzing with co-simulation is applicable to cross-level processor verification. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing

[5] The VexRiscv study reports that the misa CSR allowed arbitrary values such as zero, which the paper identifies as illegal because the complete instruction set may not be disabled. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing