Overview

Niklas Bruns is listed as an author of "Cross-Level Processor Verification via Endless Randomized Instruction Stream Generation with Coverage-guided Aging", together with Vladimir Herdt, Eyck Jentzsch, and Rolf Drechsler. The paper metadata places Bruns at the Institute of Computer Science, University of Bremen, Bremen, Germany, and gives the contact address nbruns@uni-bremen.de. [C1]

Research context

The cited work addresses cross-level processor verification at the Register-Transfer Level (RTL). Its abstract describes a randomized, coverage-guided instruction stream generator that produces a single endless and unrestricted instruction stream which evolves dynamically at runtime. [C2]

The approach uses an Instruction Set Simulator (ISS) as a reference model in a tight co-simulation setting for the RTL processor under test. Coverage information is continuously updated from the ISS execution state, and the method applies Coverage-guided Aging to smooth the coverage distribution of the randomized instruction stream over time. [C2]

Reported application

The paper reports a case study on an industrial pipelined 32-bit RISC-V processor and states that the results demonstrate the effectiveness of the approach for finding intricate corner-case bugs in RTL processor designs. [C2]

Related evidence from Bruns' earlier work on "Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing" reports that a fuzzing methodology found 24 bugs in the VexRiscv RTL core. That work also states that coverage-guided fuzzing combined with co-simulation is applicable to cross-level processor verification, and that optimized fuzzing mutations significantly improved verification results. [C3]

One reported example from the VexRiscv study concerned the misa control and status register: the paper states that the CSR allowed arbitrary values such as zero, which is illegal because the complete instruction set is not allowed to be disabled. [C4]