2026-06-08
5 items 217 entities 288 connections
Processed 61 entities and 63 relations.
ProcessorFuzz DIFUZZRTL Coverage-based Greybox Fuzzing CSR-transition coverage register coverage differential testing ISA simulation RTL simulation multiplexer toggle coverage random instruction generation coverage-directed test generation Control and Status Registers Finite State Machine seed corpus mutation engine Transition Map Transition Unit extended ISA trace log assembly program test inputs pre-silicon verification hardware fuzzing Register-Transfer Level ISA specification privilege mode Time-to-Exposure Spike ISA simulator Verilator Dromajo RFUZZ TheHuzz Cadence ModelSim Rocket Chip SoC Generator Rocket Core BOOM Core BlackParrot Core RISC-V Hardware Description Language Chisel HDL SystemVerilog HDL MulDiv module remainder register mstatus CSR fflags CSR mcause CSR medeleg CSR instret CSR sepc CSR Physical Memory Protection page table formal verification Boston University University of Washington Sadullah Canakci Chathura Rajapaksha Leila Delshadtehrani Anoop Nataraja Michael Bedford Taylor Manuel Egele Ajay Joshi ProcessorFuzz paper
Processed 54 entities and 94 relations.
CHERI RISC-V TestRIG QuickCheckVEngine RVFI-DII Piccolo Flute Toooba RiscyOO Bluespec spatial memory safety temporal memory safety sweeping revocation capability hardware security superscalar out-of-order processor merged register file FPGA prototyping Direct Instruction Injection Physical Memory Protection Memory Management Unit Program Counter Capability tag controller CHERI Capability Library Sail CHERI-RISC-V BlueStuff CHERI-Concentrate Sentry mechanism CHERIvoke microcontroller RISC-V Formal Interface bounds checking instruction pipeline UCAM-CL-TR-984 Peter David Rugg University of Cambridge Computer Laboratory DARPA Instruction Set Architecture Return-Oriented Programming capability mode bit safe speculation shadow bitmap MiBench CoreMark SPEC Vivado MIPS architecture Morello linear capabilities indirect capabilities prefetching virtual memory cache coherence RISC-V BOOM Memory Protection Unit
Processed 19 entities and 22 relations.
Test Program Generation for a Microprocessor: A Case-Study Achim D. Brucker Abderrahmane Feliachi Yakoub Nemouchi Burkhart Wolff Test Program Generation Symbolic Test Case Generation Black Box Testing White Box Testing Model-Based Testing Conformance Test Scenarios Formal Microprocessor Model Instruction Set Verification Hardware-in-the-Loop Testing Common Criteria EAL 7 Theorem Proving HOL-TestGen Isabelle/HOL Springer-Verlag
Processed 43 entities and 61 relations.
FISACO OneSpin 360 MV Interval Property Checking Bounded Model Checking Completeness Analysis Automatic Property Generation k-induction SAT-based Formal Verification Pipeline Modeling Data Path Modeling Architecture Description Mapping Functions Consistency Assertions Instruction Set Simulator Generation Theorem Proving Register Transfer Level Instruction Set Architecture Property Suite Multicycle Instructions Pipeline Hazards Branch Prediction Exceptions and Interrupts Register Forwarding Finite State Machine Safety Properties Transaction Level Model Design Under Verification Simulation-Based Verification Invariant Generation Advanced Automation in Formal Verification of Processors Ulrich Kühne Sven Beyer Jörg Bormann John Barstow OneSpin Solutions GmbH Infineon Technologies University of Bremen LSV ENS de Cachan LISA Facile Peripheral Control Processor Interface Transactions Architecture Description Language
Processed 40 entities and 48 relations.
Instruction Set Simulator Coverage-guided Fuzzing libFuzzer AFL RISC-V Spike Forvis RISC-V Virtual Prototype RISC-V Torture Test Generator RISC-V ISA Tests Functional Coverage Code Coverage Mutation-based Fuzzing Model-based Test Generation Instruction Set Architecture Constrained Random Verification ELF Binary Branch Coverage Custom Mutation Procedure Instruction Sequence Control and Status Register Illegal Instruction Handling Simulation-based Verification Vladimir Herdt Daniel Große Hoang M. Le Rolf Drechsler University of Bremen DFKI GmbH Verifying Instruction Set Simulators using Coverage-guided Fuzzing Dynamic Program Analysis SMT Solver Bayesian Network Test Generation Machine Learning for Fuzzing RV32IMA Instruction Decoder Register File In-process Fuzzing LLVMFuzzerTestOneInput Coverage-guided Fuzzing