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Ulrich Kühne

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Ulrich Kühne is listed as an author of the paper "Generating an Efficient Instruction Set Simulator from a Complete Property Suite" and is affiliated in that source with the Institute of Computer Science at the University of Bremen in Germany.

First seen 5/26/2026
Last seen 6/8/2026
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Overview

Ulrich Kühne is named as an author of the technical paper "Generating an Efficient Instruction Set Simulator from a Complete Property Suite". In the paper's author block, he is associated with the Institute of Computer Science, University of Bremen, located in Bremen, Germany, and the contact email shown for him is ulrichk@informatik.uni-bremen.de. [C1]

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University of Bremen part of → 100% 3e
The work was carried out jointly by the group for computer architecture at University of Bremen.
Ulrich Kühne is listed as an author of the paper.
Ulrich Kühne is listed as an author of the paper and his PhD thesis is the basis of the work.
LSV ENS de Cachan part of → 95% 1e
Ulrich Kühne is listed with affiliation LSV ENS de Cachan.

CITATIONS

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[1] Ulrich Kühne is listed with the Institute of Computer Science, University of Bremen, Bremen, Germany, and the email ulrichk@informatik.uni-bremen.de. Generating an Efficient Instruction Set Simulator from a Complete Property Suite
[2] Ulrich Kühne coauthored the paper "Generating an Efficient Instruction Set Simulator from a Complete Property Suite" with Sven Beyer and Christian Pichler. Generating an Efficient Instruction Set Simulator from a Complete Property Suite
[3] The paper presents an approach to automatically generate an instruction set simulator from a complete property suite used for formal verification, aiming to avoid inconsistencies between simulator, design, and ISA. Generating an Efficient Instruction Set Simulator from a Complete Property Suite
[4] The paper reports feasibility on an industrial design and states that the generated simulator's performance was comparable to custom state-of-the-art simulators. Generating an Efficient Instruction Set Simulator from a Complete Property Suite
[5] The paper describes instruction set simulators as useful for early processor software development and testing, while gate-level simulation is cycle-accurate but typically too slow and unavailable in early ISA-only design phases. Generating an Efficient Instruction Set Simulator from a Complete Property Suite
[6] The paper states that formal verification can help eliminate discrepancies between ISA and design and identifies Interval Property Checking as a technique used to check whether a design satisfies a set of properties. Generating an Efficient Instruction Set Simulator from a Complete Property Suite