Overview

Ulrich Kühne is named as an author of the technical paper "Generating an Efficient Instruction Set Simulator from a Complete Property Suite". In the paper's author block, he is associated with the Institute of Computer Science, University of Bremen, located in Bremen, Germany, and the contact email shown for him is ulrichk@informatik.uni-bremen.de. [C1]

Publication

Generating an Efficient Instruction Set Simulator from a Complete Property Suite

Kühne coauthored "Generating an Efficient Instruction Set Simulator from a Complete Property Suite" with Sven Beyer and Christian Pichler. [C2]

The paper addresses the generation of an instruction set simulator (ISS) from a complete property suite used for formal verification of a processor. Its stated motivation is that manually re-implementing an instruction set architecture for a simulator can create a risk that the simulator, the design, and the ISA become inconsistent. The paper presents an approach intended to produce a provably correct simulator with relatively small effort. [C3]

The abstract reports that the approach was evaluated on an industrial design and that the resulting simulator's performance was comparable to custom state-of-the-art simulators. [C4]

Technical context

The paper describes ISS tools as useful for early software development and testing before a processor is manufactured. It contrasts ISS performance and early availability with gate-level simulation, which is described as cycle-accurate but typically too slow for in-depth software testing and unavailable in early design phases when only the ISA is present. [C5]

The paper also emphasizes formal verification as a way to reduce discrepancies between the ISA and the processor design, mentioning Interval Property Checking as one formal hardware verification technique used to check whether a design satisfies a set of properties. [C6]