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Sven Beyer

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Sven Beyer is identified in the available evidence as a co-author of the technical paper “Generating an Efficient Instruction Set Simulator from a Complete Property Suite,” associated in the publication header with OneSpin Solutions GmbH. The paper concerns automatic generation of instruction set simulators from complete property suites used in formal processor verification.

First seen 5/26/2026
Last seen 6/8/2026
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Sven Beyer

Sven Beyer is named as a co-author of the paper “Generating an Efficient Instruction Set Simulator from a Complete Property Suite”, alongside Ulrich Kühne and Christian Pichler. The publication header lists OneSpin Solutions GmbH among the author affiliations and provides an email address for Sven Beyer in the onespin-solutions.com domain.

Technical publication

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RELATIONSHIPS

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OneSpin Solutions GmbH part of → 100% 3e
Sven Beyer is listed with affiliation OneSpin Solutions GmbH.
Sven Beyer is listed as an author of the paper.
Sven Beyer is listed as a co-author of the paper.

CITATIONS

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5 citations — click to expand
[1] Sven Beyer is listed as an author of “Generating an Efficient Instruction Set Simulator from a Complete Property Suite,” with Ulrich Kühne and Christian Pichler. Generating an Efficient Instruction Set Simulator from a Complete Property Suite
[2] The publication header lists OneSpin Solutions GmbH among the author affiliations and provides an onespin-solutions.com email address group including Sven.Beyer. Generating an Efficient Instruction Set Simulator from a Complete Property Suite
[3] The paper presents an approach for automatically generating an instruction set simulator from a complete property suite used for formal processor verification. Generating an Efficient Instruction Set Simulator from a Complete Property Suite
[4] The paper states that the generated simulator is intended to be provably correct with relatively small effort and reports feasibility on an industrial design with performance comparable to custom state-of-the-art simulators. Generating an Efficient Instruction Set Simulator from a Complete Property Suite
[5] The paper describes instruction set simulators as useful for early processor software development and testing, while noting limitations of gate-level simulation for in-depth testing and early design phases. Generating an Efficient Instruction Set Simulator from a Complete Property Suite