OneSpin Solutions GmbH

Organization

OneSpin Solutions GmbH is identified in the provided evidence as a Munich, Germany organization associated with Sven Beyer and Christian Pichler. The evidence comes from the paper “Generating an Efficient Instruction Set Simulator from a Complete Property Suite,” which presents a formal-verification-based approach for generating instruction set simulators from complete property suites.

First seen 5/26/2026

Last seen 6/8/2026

Evidence 7 chunks

Wiki v2

WIKI

Overview

OneSpin Solutions GmbH is listed in the paper Generating an Efficient Instruction Set Simulator from a Complete Property Suite with the address Theresienhöhe 12, 80339 Munich, Germany. In the paper's author block, Sven Beyer and Christian Pichler are associated with OneSpin Solutions GmbH, while Ulrich Kühne is associated with the Institute of Computer Science at the University of Bremen.

Research context

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NEIGHBORHOOD

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RELATIONSHIPS

5 connections

Sven Beyer ← part of 100% 3e

Sven Beyer is listed with affiliation OneSpin Solutions GmbH.

OneSpin IPC Verification Tool ← part of 90% 2e

OneSpin Solutions GmbH develops and offers the IPC verification tool commercially.

Christian Pichler ← part of 100% 1e

Christian Pichler is affiliated with OneSpin Solutions GmbH.

Jörg Bormann ← part of 95% 1e

Jörg Bormann is listed with affiliation OneSpin Solutions GmbH.

Advanced Automation in Formal Verification of Processors ← published by 75% 1e

The paper was jointly produced by OneSpin Solutions GmbH and University of Bremen.

LINKED ENTITIES

3 links

Sven Beyer PART_OF Extracted graph relationship

Christian Pichler PART_OF Extracted graph relationship

OneSpin IPC Verification Tool PART_OF Extracted graph relationship

CITATIONS

8 sources

8 citations — click to expand

[1] OneSpin Solutions GmbH is listed at Theresienhöhe 12, 80339 Munich, Germany, and Sven Beyer and Christian Pichler are associated with it in the paper's author block. Generating an Efficient Instruction Set Simulator from a Complete Property Suite

[2] The paper presents an approach to automatically generate an instruction set simulator from a complete property suite used for formal processor verification. Generating an Efficient Instruction Set Simulator from a Complete Property Suite

[3] The paper explains that separately implemented instruction set simulators can diverge from the ISA or processor design, creating a risk of software behaving correctly in simulation but not on chip. Generating an Efficient Instruction Set Simulator from a Complete Property Suite

[4] Interval Property Checking is described as a formal verification technique related to Bounded Model Checking and used to check whether a design satisfies a set of properties. Generating an Efficient Instruction Set Simulator from a Complete Property Suite

[5] Completeness analysis is described as determining whether every possible input scenario can be covered by a chain of properties that predicts states and outputs over time. Generating an Efficient Instruction Set Simulator from a Complete Property Suite

[6] The properties are written in ITL, where temporal logic expressions describe the behavior of a synchronous sequential system. Generating an Efficient Instruction Set Simulator from a Complete Property Suite

[7] In the industrial-design experiment, the processor core was about 10,000 lines of VHDL, the reformulated property suite was about 2,000 lines of ITL, and the property suite and completeness were successfully checked against the processor design. Generating an Efficient Instruction Set Simulator from a Complete Property Suite

[8] For the industrial design, the commercial just-in-time compiled simulator averaged 2.5 MIPS and the generated ISS reached 1.2 MIPS; the paper states that the generated ISS performance was comparable to modern custom-made instruction set simulators. Generating an Efficient Instruction Set Simulator from a Complete Property Suite