OneSpin IPC Verification Tool

Tool

The OneSpin IPC Verification Tool is associated with a commercial Interval Property Checking (IPC) verification environment used for formal hardware verification. In the cited ISS-generation work, an IPC-based environment with integrated completeness analysis was used to check that a processor property suite was correct and complete before generating an instruction set simulator from it.

First seen 5/29/2026

Last seen 5/29/2026

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Overview

The OneSpin IPC Verification Tool is a formal verification tool associated with Interval Property Checking (IPC). In the available evidence, IPC is described as a SAT-based formal verification methodology used to check whether a hardware design satisfies a set of properties written in a dedicated verification language. The same source states that completeness analysis integrated within an IPC verification environment was commercially available.

Verification method

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RELATIONSHIPS

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OneSpin Solutions GmbH part of → 90% 2e

OneSpin Solutions GmbH develops and offers the IPC verification tool commercially.

Generating an Efficient Instruction Set Simulator from a Complete Property Suite ← uses 95% 1e

The paper uses the OneSpin IPC verification tool for completeness analysis.

Interval Property Checking implements → 95% 1e

The OneSpin tool is a commercial IPC verification environment.

Completeness Analysis uses → 95% 1e

The OneSpin tool integrates completeness analysis within its verification environment.

LINKED ENTITIES

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Generating an Efficient Instruction Set Simulator from a Complete Property Suite USES Extracted graph relationship

Interval Property Checking IMPLEMENTS Extracted graph relationship

Completeness Analysis USES Extracted graph relationship

OneSpin Solutions GmbH PART_OF Extracted graph relationship

CITATIONS

7 sources

7 citations — click to expand

[1] IPC is a technique similar to Bounded Model Checking and is used to check whether a design satisfies a set of properties written in a dedicated verification language. Generating an Efficient Instruction Set Simulator from a Complete Property Suite

[2] IPC verifies safety properties from arbitrary starting states and may require invariants to remove false negatives from unreachable states. Generating an Efficient Instruction Set Simulator from a Complete Property Suite

[3] Completeness analysis integrated within an IPC verification environment was commercially available and checks whether every possible input scenario can be covered by a chain of properties predicting states and outputs. Generating an Efficient Instruction Set Simulator from a Complete Property Suite

[4] Completeness analysis checks successor-property existence, uniqueness, and unique description of outputs and states; any two designs satisfying a complete property suite are formally equivalent. Generating an Efficient Instruction Set Simulator from a Complete Property Suite

[5] The cited work proposes automatically generating an instruction set simulator from a complete property suite used for formal processor verification. Generating an Efficient Instruction Set Simulator from a Complete Property Suite

[6] A processor property suite and its completeness were successfully checked against the design using the referenced commercial environment, and the generated ISS reached 7.0 MIPS for a simple processor and 1.2 MIPS for an industrial design. Generating an Efficient Instruction Set Simulator from a Complete Property Suite

[7] The paper includes authors affiliated with OneSpin Solutions GmbH. Generating an Efficient Instruction Set Simulator from a Complete Property Suite