Completeness Analysis
ConceptCompleteness analysis is a formal-verification technique for determining whether a property suite covers every possible input scenario of a design and uniquely predicts states and outputs over time. In the cited processor-verification context, a complete property suite can serve as a model of the verified design, enabling uses such as generating an executable simulator.
First seen 5/26/2026
Last seen 5/29/2026
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Definition
Completeness analysis determines whether every possible input scenario of a design—described as a transaction sequence—can be covered by a chain of properties that predicts the values of states and outputs at every point in time. A property suite that passes this analysis is considered complete in the sense that any two designs satisfying all properties in the suite are formally equivalent. [C1]
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4 connectionsCompleteness analysis is used to verify that a property suite is complete.
Completeness analysis is integrated within the IPC verification environment.
IPC uses completeness analysis to determine whether the property suite covers all behaviors.
The OneSpin tool integrates completeness analysis within its verification environment.
LINKED ENTITIES
2 linksComplete Property Suite evaluates The evidence states that completeness analysis determines whether a set or suite of properties forms a complete specification and that complete property suites imply formal equivalence of designs satisfying them.
Instruction Set Simulator enables_generation_of The evidence states that a complete property suite can be exploited to obtain an executable model and describes generating an ISS from such a suite.
CITATIONS
9 sources9 citations — click to expand
[1] Completeness analysis determines whether every possible input scenario can be covered by a chain of properties that predicts states and outputs over time, and any two designs fulfilling a complete property suite are formally equivalent. Generating an Efficient Instruction Set Simulator from a Complete Property Suite
[2] Completeness analysis checks for a matching successor property, a uniquely determined successor property, and unique description of outputs and states for the DUV. Generating an Efficient Instruction Set Simulator from a Complete Property Suite
[3] The cited verification flow uses interval property checking, a SAT-based method for safety properties that uses arbitrary starting states and may require invariants to remove false negatives from unreachable states. Generating an Efficient Instruction Set Simulator from a Complete Property Suite
[4] Completeness analysis integrated within an IPC verification environment was commercially available according to the cited paper. Generating an Efficient Instruction Set Simulator from a Complete Property Suite
[5] If verification is completed successfully, the property suite forms a model of the verified design by uniquely describing transitions and output behavior. Generating an Efficient Instruction Set Simulator from a Complete Property Suite
[6] The model character of a verified complete property suite, together with abstraction, can be exploited to obtain a simulator capturing the entire design behavior. Generating an Efficient Instruction Set Simulator from a Complete Property Suite
[7] In the cited case study, a processor core of about 10,000 lines of VHDL had a final reformulated property suite of about 2,000 lines of ITL, and the suite and its completeness were checked against the processor design. Generating an Efficient Instruction Set Simulator from a Complete Property Suite
[8] For an industrial design, the generated ISS reached 1.2 MIPS versus 2.5 MIPS for a commercial just-in-time compiled simulator, supporting the authors' conclusion that generated ISS performance was comparable to modern custom-made ISSs. Generating an Efficient Instruction Set Simulator from a Complete Property Suite
[9] The cited properties are written in ITL, where temporal-logic expressions describe synchronous sequential-system behavior and discrete time steps correspond to clock cycles. Generating an Efficient Instruction Set Simulator from a Complete Property Suite