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OneSpin Solutions GmbH

Organization WIKI v2 · 5/29/2026

OneSpin Solutions GmbH is identified in the provided evidence as a Munich, Germany organization associated with Sven Beyer and Christian Pichler. The evidence comes from the paper “Generating an Efficient Instruction Set Simulator from a Complete Property Suite,” which presents a formal-verification-based approach for generating instruction set simulators from complete property suites.

Overview

OneSpin Solutions GmbH is listed in the paper Generating an Efficient Instruction Set Simulator from a Complete Property Suite with the address Theresienhöhe 12, 80339 Munich, Germany. In the paper's author block, Sven Beyer and Christian Pichler are associated with OneSpin Solutions GmbH, while Ulrich Kühne is associated with the Institute of Computer Science at the University of Bremen.

Research context

The cited paper focuses on instruction set simulators (ISS) used in processor and system design flows. It explains that ISS tools support early software development and testing before a processor is manufactured, but that separately implemented simulators can diverge from the instruction set architecture (ISA) or from the final hardware design.

The paper presents an approach for automatically generating an ISS from a complete property suite used in formal processor verification. The stated aim is to derive the simulator from the ISA as used in verification, reducing the risk of discrepancies between the simulator, the ISA, and the processor design.

Formal-verification relevance

The paper describes Interval Property Checking (IPC) as a formal hardware-verification technique related to Bounded Model Checking. IPC is used to check whether a design satisfies properties written in a dedicated verification language. The paper also describes completeness analysis: a complete property suite should cover every possible input scenario as a chain of properties that predicts states and outputs over time.

The properties in the paper are written in ITL, where temporal-logic expressions describe the behavior of a synchronous sequential system. In the reported industrial-design experiment, the processor core source code was about 10,000 lines of VHDL and the reformulated property suite was about 2,000 lines of ITL. The paper reports that the property suite and its completeness were successfully checked against the processor design.

Reported simulator results

For the industrial design discussed in the evidence, a commercial just-in-time compiled simulator averaged 2.5 MIPS, while the ISS generated by the paper's approach reached 1.2 MIPS. The paper states that these results support the conclusion that the generated ISS achieved performance comparable to modern custom-made instruction set simulators, while noting that the custom JIT-CS simulators were still faster.

LINKED ENTITIES

3 links
Sven Beyer PART_OF
Christian Pichler PART_OF
OneSpin IPC Verification Tool PART_OF

CITATIONS

8 sources
8 citations
[1] OneSpin Solutions GmbH is listed at Theresienhöhe 12, 80339 Munich, Germany, and Sven Beyer and Christian Pichler are associated with it in the paper's author block. Generating an Efficient Instruction Set Simulator from a Complete Property Suite
[2] The paper presents an approach to automatically generate an instruction set simulator from a complete property suite used for formal processor verification. Generating an Efficient Instruction Set Simulator from a Complete Property Suite
[3] The paper explains that separately implemented instruction set simulators can diverge from the ISA or processor design, creating a risk of software behaving correctly in simulation but not on chip. Generating an Efficient Instruction Set Simulator from a Complete Property Suite
[4] Interval Property Checking is described as a formal verification technique related to Bounded Model Checking and used to check whether a design satisfies a set of properties. Generating an Efficient Instruction Set Simulator from a Complete Property Suite
[5] Completeness analysis is described as determining whether every possible input scenario can be covered by a chain of properties that predicts states and outputs over time. Generating an Efficient Instruction Set Simulator from a Complete Property Suite
[6] The properties are written in ITL, where temporal logic expressions describe the behavior of a synchronous sequential system. Generating an Efficient Instruction Set Simulator from a Complete Property Suite
[7] In the industrial-design experiment, the processor core was about 10,000 lines of VHDL, the reformulated property suite was about 2,000 lines of ITL, and the property suite and completeness were successfully checked against the processor design. Generating an Efficient Instruction Set Simulator from a Complete Property Suite
[8] For the industrial design, the commercial just-in-time compiled simulator averaged 2.5 MIPS and the generated ISS reached 1.2 MIPS; the paper states that the generated ISS performance was comparable to modern custom-made instruction set simulators. Generating an Efficient Instruction Set Simulator from a Complete Property Suite

VERSION HISTORY

v2 · 5/29/2026 · gpt-5.5 (current)
v1 · 5/26/2026 · gpt-5.5