Sven Beyer

Sven Beyer is named as a co-author of the paper “Generating an Efficient Instruction Set Simulator from a Complete Property Suite”, alongside Ulrich Kühne and Christian Pichler. The publication header lists OneSpin Solutions GmbH among the author affiliations and provides an email address for Sven Beyer in the onespin-solutions.com domain.

Technical publication

In the cited paper, the authors present an approach for automatically generating an instruction set simulator (ISS) from a complete property suite used for formal processor verification. The abstract states that this method is intended to produce a simulator that is provably correct relative to the verified instruction-set properties, while requiring relatively small effort. The paper also reports feasibility on an industrial design and states that the resulting simulator performance is comparable to custom state-of-the-art simulators.

Research context

The paper situates the work in processor and system design flows, where instruction set simulators are used for early software development and testing before a processor is manufactured. It contrasts ISS-based simulation with gate-level simulation, noting that gate-level simulation can be cycle-accurate but is generally too slow for extensive software testing and may not be available early in the design process. The paper motivates deriving an ISS from the same ISA properties used in formal verification to reduce discrepancies between the simulator, the ISA, and the processor design.