Abderrahmane Feliachi

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Abderrahmane Feliachi is listed as a co-author of the 2013 paper "Test Program Generation for a Microprocessor: A Case-Study" and as affiliated with Univ. Paris-Sud, Laboratoire LRI, UMR8623, in Orsay, France. The paper reports a case study on generating microprocessor test programs from formal models using Isabelle/HOL and HOL-TestGen.

First seen 5/25/2026

Last seen 6/8/2026

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Abderrahmane Feliachi

Abderrahmane Feliachi is named as a co-author of the technical paper Test Program Generation for a Microprocessor: A Case-Study, alongside Achim D. Brucker, Yakoub Nemouchi, and Burkhart Wolff. [C1]

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Test Program Generation for a Microprocessor: A Case-Study ← authored by 100% 2e

The paper is authored by Abderrahmane Feliachi.

Université Paris-Sud part of → 100% 1e

Abderrahmane Feliachi is affiliated with Université Paris-Sud.

CNRS part of → 100% 1e

Abderrahmane Feliachi is affiliated with CNRS.

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Test Program Generation for a Microprocessor: A Case-Study AUTHORED Extracted graph relationship

Univ. Paris-Sud, Laboratoire LRI AFFILIATED_WITH Extracted graph relationship

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[1] C1: Abderrahmane Feliachi is listed as a co-author of "Test Program Generation for a Microprocessor: A Case-Study" with Achim D. Brucker, Yakoub Nemouchi, and Burkhart Wolff. Test Program Generation for a Microprocessor: A Case Study

[2] C2: The paper lists Feliachi under the affiliation Univ. Paris-Sud, Laboratoire LRI, UMR8623, Orsay, F-91405, France, and CNRS, Orsay, F-91405, France. Test Program Generation for a Microprocessor: A Case Study

[3] C3: The author version states that the paper appeared in TAP 2013, LNCS 7942, pages 76–95, published by Springer-Verlag in 2013. Test Program Generation for a Microprocessor: A Case Study

[4] C4: The paper presents a case study that uses a formal model of a microprocessor to generate test programs that validate correct implementation of the specified instruction set. Test Program Generation for a Microprocessor: A Case Study

[5] C5: The case study uses an existing Isabelle/HOL model and HOL-TestGen, and reports conformance test scenarios in which synthesized test programs were run against real hardware in the loop. Test Program Generation for a Microprocessor: A Case Study