RISC-V ISA Tests

Tool

RISC-V ISA Tests are a hand-written directed RISC-V test suite referenced at github.com/riscv/riscv-tests and used as a baseline in a coverage-guided fuzzing study of RISC-V instruction-set simulators.

First seen 5/28/2026

Last seen 6/8/2026

Evidence 10 chunks

Wiki v3

WIKI

Overview

RISC-V ISA Tests are a RISC-V test suite cited by Verifying Instruction Set Simulators using Coverage-guided Fuzzing with the repository URL https://github.com/riscv/riscv-tests. In that study, the suite is treated as a set of directed tests that are hand-written and therefore do not require a test-generation step.

Use in simulator verification

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NEIGHBORHOOD

2 nodes · 1 edges

graph · RISC-V ISA Tests · depth=1

RELATIONSHIPS

4 connections

Verifying Instruction Set Simulators using Coverage-guided Fuzzing ← uses 100% 4e

The paper integrates RISC-V ISA Tests for comparison in the evaluation.

Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing ← compares with 70% 2e

The paper mentions RISC-V ISA Tests as a related baseline verification approach.

Verifying Instruction Set Simulators using Coverage-guided Fuzzing ← compares with 100% 2e

The paper compares its CGF approach against the RISC-V ISA tests.

RISC-V uses → 90% 1e

RISC-V ISA Tests are directed tests for the RISC-V ISA.

LINKED ENTITIES

2 links

Verifying Instruction Set Simulators using Coverage-guided Fuzzing USES Extracted graph relationship

RISC-V USES Extracted graph relationship

CITATIONS

5 sources

5 citations — click to expand

[1] RISC-V ISA Tests are cited with the repository URL https://github.com/riscv/riscv-tests. Verifying Instruction Set Simulators using Coverage-guided Fuzzing

[2] The paper treats RISC-V ISA Tests as hand-written directed tests that do not require a generation step. Verifying Instruction Set Simulators using Coverage-guided Fuzzing

[3] The evaluation table reports RISC-V ISA Tests with a time of 2 seconds, 90.24% branch coverage, listed functional-coverage values, and [V1..V3] errors found in the ISS under test. Verifying Instruction Set Simulators using Coverage-guided Fuzzing

[4] The paper compares RISC-V ISA Tests against RISC-V Torture-generated test sets and a coverage-guided fuzzing approach. Verifying Instruction Set Simulators using Coverage-guided Fuzzing

[5] The paper concludes that its LLVM-libFuzzer-based coverage-guided fuzzing approach was evaluated on three publicly available RISC-V ISSs and was effective in maximizing most coverage metrics and finding errors. Verifying Instruction Set Simulators using Coverage-guided Fuzzing