RISC-V Virtual Prototype

Tool

The RISC-V Virtual Prototype is a publicly available, MIT-licensed RISC-V virtual platform implemented in standard-compliant SystemC and TLM-2.0. Evidence describes it as an extensible and configurable platform with a generic bus, an RV32IMA core, a PLIC-based interrupt controller, and essential peripherals; its extracted ISS was used as the system under test in a coverage-guided fuzzing study.

First seen 5/28/2026

Last seen 6/8/2026

Evidence 7 chunks

Wiki v1

WIKI

Overview

The RISC-V Virtual Prototype is a publicly available RISC-V virtual platform referenced by the GitHub project agra-uni-bremen/riscv-vp. The available evidence describes the VP as implemented in standard-compliant SystemC and TLM-2.0, designed as an extensible and configurable platform with a generic bus system. It integrates a RISC-V RV32IMA core, a PLIC-based interrupt controller, and an essential set of peripherals, and is available under the MIT license. [C1]

Role in RISC-V ISS verification

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NEIGHBORHOOD

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RELATIONSHIPS

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Verifying Instruction Set Simulators using Coverage-guided Fuzzing ← evaluates 100% 4e

The paper evaluates the RISC-V Virtual Prototype as the ISS under test.

RISC-V implements → 100% 2e

The RISC-V Virtual Prototype implements a RISC-V RV32IMA core.

Instruction Set Architecture implements → 100% 2e

The RISC-V Virtual Prototype implements the RISC-V ISA.

Instruction Set Simulator implements → 100% 1e

The RISC-V Virtual Prototype contains an ISS for RV32IMA.

LINKED ENTITIES

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Verifying Instruction Set Simulators using Coverage-guided Fuzzing EVALUATES Extracted graph relationship

Instruction Set Architecture IMPLEMENTS Extracted graph relationship

CITATIONS

4 sources

4 citations — click to collapse

[1] The RISC-V Virtual Prototype is publicly referenced at the agra-uni-bremen/riscv-vp GitHub project, is implemented in standard-compliant SystemC and TLM-2.0, is extensible and configurable with a generic bus, integrates an RV32IMA core, a PLIC-based interrupt controller, and essential peripherals, and is available under the MIT license. Verifying Instruction Set Simulators using Coverage-guided Fuzzing

[2] The paper used the RV32IMA ISS extracted from the publicly available RISC-V Virtual Prototype as the ISS under test, denoted ISS-UT, with Spike and Forvis as reference ISSs. Verifying Instruction Set Simulators using Coverage-guided Fuzzing

[3] The ISS-UT was instrumented for branch coverage with clang and for functional coverage using begin-fcov-trace and end-fcov-trace calls around instruction execution, capturing instruction, decoded operation, and register-state snapshots. Verifying Instruction Set Simulators using Coverage-guided Fuzzing

[4] The coverage-guided fuzzing study was implemented on top of LLVM libFuzzer, evaluated on three publicly available RISC-V ISSs, and reported 100% branch coverage and all seven listed ISS-UT errors found for the coverage-guided fuzzing run, along with errors in Spike and Forvis. Verifying Instruction Set Simulators using Coverage-guided Fuzzing