Transaction Level Modeling

Concept

Transaction Level Modeling (TLM) is used with SystemC to model communication at a higher level of abstraction than signal-level RTL. In the provided processor-verification evidence, TLM transactions carry commands such as read/write, payload data, and addresses, and are used to provide a unified memory abstraction between an RTL core and an instruction-set simulator in a co-simulation testbench.

First seen 5/25/2026

Last seen 6/9/2026

Evidence 6 chunks

Wiki v1

WIKI

Overview

Transaction Level Modeling (TLM) is identified in the evidence as part of a SystemC-based modeling approach for building designs at different levels of abstraction. The cited processor-verification work states that its co-simulation testbench is implemented in SystemC and uses TLM. In that context, communication may be implemented either through signals, commonly used for RTL models, or through TLM transactions, commonly used for high-level algorithmic models.

Transaction structure

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NEIGHBORHOOD

2 nodes · 1 edges

graph · Transaction Level Modeling · depth=1

RELATIONSHIPS

3 connections

UVM environment ← uses 90% 1e

The UVM environment uses transaction-level modeling for communication between components.

SimSoC ← uses 95% 1e

SimSoC uses transaction level modeling for module communications

Class-Based Testbench ← implements 90% 1e

Class-Based Testbench implements transaction-level modeling by using classes to represent abstract data transactions.

LINKED ENTITIES

1 links

Co-Simulation Testbench USES Extracted graph relationship

CITATIONS

8 sources

8 citations — click to expand

[1] The cited co-simulation testbench is implemented in SystemC and uses TLM. 2020FDL_cross-level-processor-verification-riscv.pdf

[2] SystemC combined with TLM is described as an industry-proven modeling standard for building designs at different abstraction levels. 2020FDL_cross-level-processor-verification-riscv.pdf

[3] Communication can be implemented via signals for RTL models or abstracted using TLM transactions for high-level algorithmic models. 2020FDL_cross-level-processor-verification-riscv.pdf

[4] A TLM transaction object essentially consists of a command, payload data, and an address. 2020FDL_cross-level-processor-verification-riscv.pdf

[5] The example memory interface receives a TLM generic payload, obtains address, access length, and data pointer from it, and performs a read or write based on the TLM command. 2020FDL_cross-level-processor-verification-riscv.pdf

[6] In the cited testbench, memory interfaces translate between RTL core signals and TLM transactions. 2020FDL_cross-level-processor-verification-riscv.pdf

[7] TLM transactions are used to provide a unified memory abstraction for the RTL core and the ISS. 2020FDL_cross-level-processor-verification-riscv.pdf

[8] The co-simulation testbench executes one instruction on the RTL core, executes the same instruction on the ISS, and compares execution states, especially registers. 2020FDL_cross-level-processor-verification-riscv.pdf