2026-06-09
5 items 142 entities 163 connections
Processed 54 entities and 62 relations.
DIFUZZRTL Register-Coverage Guided Fuzzing Differential Fuzzing Coverage-Guided Fuzzing Mux-Coverage Guided Fuzzing Cycle-Sensitive Register Coverage SimInput Input Stimuli Per-Instruction Mutation Interrupt Mutation Asynchronous Interrupt Handling Backward Data-Flow Analysis Finite State Machine (FSM) RTL Design ISA Simulation RTL Simulation Golden Model Control Register Multiplexer (Mux) System-on-Chip (SoC) TileLink Protocol RFuzz Verilator Icarus Verilog cocotb FireSim Pyverilog FIRRTL Compiler AFL RISC-V ISA OpenRISC ISA RISC-V Rocket Core RISC-V BOOM Core OpenRISC Mor1kx Cappuccino Pseudo Interrupt Controller Pseudo Memory Unit Stimuli Generation Drop-in-Replacement Design Instruction Set Architecture (ISA) Register-Transfer Level (RTL) Verilog VHDL Chisel HDL FPGA Emulation Jaewon Hur Suhwan Song Dongup Kwon Eunjin Baek Jangwoo Kim Byoungyoung Lee Seoul National University Speculative Execution Vulnerabilities Cross-Checking Execution Results DIFUZZRTL Source Code
Processed 59 entities and 76 relations.
rtlv SymbiYosys Rosette Yosys Z3 rtlv/shiva sv2v AVR Averroes deterministic start output determinism microarchitectural state clearing hybrid symbolic execution bounded model checking SMT-based formal verification performance hints push-button formal verification circuit-agnostic property checker Verilog to Rosette compiler self-equivalence with don't-cares type-driven state merging rewrite rules SMT-LIB #lang yosys Racket boot code execution PicoRV32 MicroTitan OpenTitan Ibex CPU RISC-V symbolic execution SystemVerilog Assertions Verilog SystemVerilog Noah Moroze Anish Athalye M. Frans Kaashoek Nickolai Zeldovich MIT CSAIL lowRISC Google rtlv: push-button verification of software on hardware Yosys-SMTBMC concretize hint abstract hint unsafe-custom-hint run-and-replace hint abstract-or-overapprox-vector hint flip-flop SoC RTL cycle-accurate simulation SPI peripheral USB peripheral UART peripheral Coq clock domain Cortex M0+
Randomized Testing of RISC-V CPUs Using Direct Instruction Injection - researchr publication
source →Processed 16 entities and 15 relations.
Randomized Testing of RISC-V CPUs Using Direct Instruction Injection Direct Instruction Injection Randomized Testing RISC-V CPU Alexandre Joannou Peter Rugg Jonathan Woodruff Franz A. Fuchs Marno van der Maas Matthew Naylor Michael Roe Robert N. M. Watson Peter G. Neumann Simon W. Moore IEEE Design & Test of Computers
Genesys-Pro: Innovations in test program generation for functional processor verification for IEEE Design and Test of Computers - IBM Research
source →Processed 6 entities and 5 relations.