Simon W. Moore

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Simon W. Moore is listed as a co-author of the 2023 IEEE Design & Test paper “Randomized Testing of RISC-V CPUs using Direct Instruction Injection,” which describes the TestRIG framework for randomized testing of RISC-V implementations.

First seen 5/27/2026

Last seen 6/9/2026

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Simon W. Moore

Simon W. Moore is listed as a co-author of the 2023 IEEE Design & Test paper “Randomized Testing of RISC-V CPUs using Direct Instruction Injection.” The paper’s author list includes Alexandre Joannou, Peter Rugg, Jonathan Woodruff, Franz A. Fuchs, Marno van der Maas, Matthew Naylor, Michael Roe, Robert N. M. Watson, Peter G. Neumann, and Simon W. Moore. [C1]

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Randomized Testing of RISC-V CPUs using Direct Instruction Injection ← authored by 100% 6e

Simon W. Moore is listed as an author of the paper.

Who tests the TestRIG? Tooling for randomised tandem verification ← authored by 100% 1e

Simon W. Moore is listed as an author of the paper.

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[1] Simon W. Moore is listed as a co-author of the 2023 IEEE Design & Test paper “Randomized Testing of RISC-V CPUs using Direct Instruction Injection.” Randomized Testing of RISC-V CPUs using Direct Instruction Injection

[2] The paper presents TestRIG as a testing framework for RISC-V implementations and describes the Sail formal model as human-readable and usable for simulation and verification. Randomized Testing of RISC-V CPUs using Direct Instruction Injection

[3] TestRIG checks model/implementation equivalence pragmatically by generating random instruction sequences, executing them on both systems, and comparing traces; the paper states this can demonstrate divergence but does not prove equivalence. Randomized Testing of RISC-V CPUs using Direct Instruction Injection

[4] The paper describes Direct Instruction Injection and states that TestRIG uses the RISC-V Formal Interface to observe state changes after each instruction. Randomized Testing of RISC-V CPUs using Direct Instruction Injection

[5] The authors report using TestRIG on standard RISC-V extensions and the experimental CHERI security extension, and state that it improved usability and coverage relative to instruction-set-level unit tests. Randomized Testing of RISC-V CPUs using Direct Instruction Injection