Simon W. Moore

Person WIKI v1 · 5/27/2026

Simon W. Moore is listed as a co-author of the 2023 IEEE Design & Test paper “Randomized Testing of RISC-V CPUs using Direct Instruction Injection,” which describes the TestRIG framework for randomized testing of RISC-V implementations.

Simon W. Moore

Simon W. Moore is listed as a co-author of the 2023 IEEE Design & Test paper “Randomized Testing of RISC-V CPUs using Direct Instruction Injection.” The paper’s author list includes Alexandre Joannou, Peter Rugg, Jonathan Woodruff, Franz A. Fuchs, Marno van der Maas, Matthew Naylor, Michael Roe, Robert N. M. Watson, Peter G. Neumann, and Simon W. Moore. [C1]

Associated publication

The associated publication presents TestRIG — “Testing with Random Instruction Generation” — as a testing framework for RISC-V implementations. It explains that RISC-V has a formal model in the Sail language, which provides a human-readable specification usable for simulation and verification. [C2]

The paper describes TestRIG as a pragmatic alternative to full processor-level formal equivalence proof: it generates random instruction sequences, executes the same sequences on both a model and an implementation under test, and compares execution traces in tandem execution. The authors note that this approach does not prove equivalence, but can demonstrate divergence and is usable during development. [C3]

The publication also introduces Direct Instruction Injection as a test-injection technique in which the next instruction is supplied by the test harness regardless of the CPU program counter, rather than being fetched normally from program memory. TestRIG is described as using the RISC-V Formal Interface to observe state changes after each instruction. [C4]

According to the paper, the authors used TestRIG to test many standard RISC-V extensions and the experimental CHERI security extension. They report that TestRIG was easier to use than unit tests, provided more thorough test coverage through random generation, and was effective at detecting issues in instruction semantics, pipelines, and data caches. [C5]

LINKED ENTITIES

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Randomized Testing of RISC-V CPUs using Direct Instruction Injection AUTHORED_BY

CITATIONS

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5 citations

[1] Simon W. Moore is listed as a co-author of the 2023 IEEE Design & Test paper “Randomized Testing of RISC-V CPUs using Direct Instruction Injection.” Randomized Testing of RISC-V CPUs using Direct Instruction Injection

[2] The paper presents TestRIG as a testing framework for RISC-V implementations and describes the Sail formal model as human-readable and usable for simulation and verification. Randomized Testing of RISC-V CPUs using Direct Instruction Injection

[3] TestRIG checks model/implementation equivalence pragmatically by generating random instruction sequences, executing them on both systems, and comparing traces; the paper states this can demonstrate divergence but does not prove equivalence. Randomized Testing of RISC-V CPUs using Direct Instruction Injection

[4] The paper describes Direct Instruction Injection and states that TestRIG uses the RISC-V Formal Interface to observe state changes after each instruction. Randomized Testing of RISC-V CPUs using Direct Instruction Injection

[5] The authors report using TestRIG on standard RISC-V extensions and the experimental CHERI security extension, and state that it improved usability and coverage relative to instruction-set-level unit tests. Randomized Testing of RISC-V CPUs using Direct Instruction Injection