Matthew Naylor
PersonMatthew Naylor is identified in the provided evidence as a co-author of the IEEE Design & Test paper "Randomized Testing of RISC-V CPUs using Direct Instruction Injection," which describes TestRIG, a randomized testing framework for RISC-V implementations.
First seen 5/27/2026
Last seen 6/9/2026
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Matthew Naylor
Matthew Naylor is identified in the available evidence as a co-author of the paper "Randomized Testing of RISC-V CPUs using Direct Instruction Injection". The paper's author list includes Alexandre Joannou, Peter Rugg, Jonathan Woodruff, Franz A. Fuchs, Marno van der Maas, Matthew Naylor, Michael Roe, Robert N. M. Watson, Peter G. Neumann, and Simon W. Moore.
Authored work
NEIGHBORHOOD
2 nodes · 1 edgesgraph · Matthew Naylor · depth=1
RELATIONSHIPS
1 connectionsMatthew Naylor is listed as an author of the paper.
CITATIONS
5 sources5 citations — click to expand
[1] Matthew Naylor is listed as a co-author of "Randomized Testing of RISC-V CPUs using Direct Instruction Injection". Randomized Testing of RISC-V CPUs using Direct
[2] The paper presents TestRIG as a testing framework for RISC-V implementations. Randomized Testing of RISC-V CPUs using Direct
[3] TestRIG checks equivalence by generating random instruction sequences, executing them on a model and an implementation under test, and comparing execution traces. Randomized Testing of RISC-V CPUs using Direct
[4] The paper describes using RVFI to observe state changes after each instruction and Direct Instruction Injection to supply instructions independently of the CPU program counter. Randomized Testing of RISC-V CPUs using Direct
[5] The paper states that TestRIG was used to test standard RISC-V extensions and the experimental CHERI security extension, and that it was effective at detecting issues in instruction semantics, pipelines, and data caches. Randomized Testing of RISC-V CPUs using Direct