Matthew Naylor

Person WIKI v1 · 5/27/2026

Matthew Naylor is identified in the provided evidence as a co-author of the IEEE Design & Test paper "Randomized Testing of RISC-V CPUs using Direct Instruction Injection," which describes TestRIG, a randomized testing framework for RISC-V implementations.

Matthew Naylor

Matthew Naylor is identified in the available evidence as a co-author of the paper "Randomized Testing of RISC-V CPUs using Direct Instruction Injection". The paper's author list includes Alexandre Joannou, Peter Rugg, Jonathan Woodruff, Franz A. Fuchs, Marno van der Maas, Matthew Naylor, Michael Roe, Robert N. M. Watson, Peter G. Neumann, and Simon W. Moore.

Authored work

Randomized Testing of RISC-V CPUs using Direct Instruction Injection

The paper presents TestRIG—short for Testing with Random Instruction Generation—as a testing framework for RISC-V implementations. It describes using randomized instruction sequences to compare an executable formal model with an implementation under test, executing the same sequences on both and comparing execution traces in a tandem-execution style.

The work also describes TestRIG's use of the RISC-V Formal Interface (RVFI) to observe state changes after each instruction, and introduces Direct Instruction Injection (DII), in which the test harness supplies the next instruction to execute regardless of the CPU program counter. According to the paper, this approach was used to test standard RISC-V extensions and the experimental CHERI security extension, and was found effective for detecting issues in instruction semantics, pipelines, and data caches.

LINKED ENTITIES

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Randomized Testing of RISC-V CPUs using Direct Instruction Injection AUTHORED_BY

CITATIONS

5 sources

5 citations

[1] Matthew Naylor is listed as a co-author of "Randomized Testing of RISC-V CPUs using Direct Instruction Injection". Randomized Testing of RISC-V CPUs using Direct

[2] The paper presents TestRIG as a testing framework for RISC-V implementations. Randomized Testing of RISC-V CPUs using Direct

[3] TestRIG checks equivalence by generating random instruction sequences, executing them on a model and an implementation under test, and comparing execution traces. Randomized Testing of RISC-V CPUs using Direct

[4] The paper describes using RVFI to observe state changes after each instruction and Direct Instruction Injection to supply instructions independently of the CPU program counter. Randomized Testing of RISC-V CPUs using Direct

[5] The paper states that TestRIG was used to test standard RISC-V extensions and the experimental CHERI security extension, and that it was effective at detecting issues in instruction semantics, pipelines, and data caches. Randomized Testing of RISC-V CPUs using Direct