clock domain

Concept

A clock domain is a region of a digital circuit in which all sequential elements are clocked by a single, related clock signal. In modern System-on-Chip (SoC) designs, multiple asynchronous clock domains coexist, requiring explicit handling of clock domain crossings (CDC) to avoid metastability and functional bugs.

First seen 6/9/2026

Last seen 6/9/2026

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Definition

A clock domain is a portion of a synchronous digital circuit in which every flip-flop, register, and other clocked storage element is driven by (or derived from) the same clock signal. Signals that originate in one clock domain and are consumed in another must traverse a clock domain crossing (CDC), which is susceptible to metastability if not properly synchronized.

In the rtlv case study of the MicroTitan RISC-V SoC, the authors state that "MicroTitan includes multiple clock domains that we verified separately", and the paper focuses its detailed analysis on the core clock domain.

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MicroTitan part of → 100% 2e

MicroTitan includes multiple clock domains that were verified separately.

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CITATIONS

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6 citations — click to expand

[1] MicroTitan includes multiple clock domains that were verified separately, with the case study focusing on the core clock domain. rtlv: push-button verification of software on hardware

[2] The core clock domain of MicroTitan contains the Ibex CPU, memories, UART, and slices of the SPI and USB peripherals. rtlv: push-button verification of software on hardware

[3] MicroTitan's other clock domains were also verified, but no machine-checked end-to-end proof ties the per-domain properties to a top-level output determinism property. rtlv: push-button verification of software on hardware

[4] rtlv does not support asynchronous resets or clocks derived from logic in Verilog; these can be removed, transformed, or preprocessed using Yosys's clk2fflogic pass. rtlv: push-button verification of software on hardware

[5] Modern SoC designs often operate on multiple asynchronous clock domains, and a GALS approach is commonly used to create multiple asynchronous domains, with CDC paths prone to metastability. Pragmatic Formal Verification Methodology for Clock Domain Crossing (CDC)

[6] A clock domain transfer circuit can move sampled data from one clock domain to a receiver clock domain with a maximum latency of three clock cycles. A Clock Synchronizer for Repeaterless Low Swing On-Chip Links